NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 170

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

5.12.3
5.12.3.1 Overview
5.12.3.2 Detecting a System Lockup
5.12.3.3 Handling an OS Lockup
Intel
DS
170
®
6300ESB I/O Controller Hub
Note: When the NO-REBOOT bit (D31:F0:Offset D4:bit 1) is set (no reboots are intended),
TCO Theory of Operation
The System Management functions are designed to allow the system to diagnose failing
subsystems. The intent of this logic is that some of the system management
functionality be provided without the aid of an external microcontroller.
When the processor is reset, it is expected to fetch its first instruction. When the
processor fails to fetch the first instruction after reset, the TCO timer will timeout twice
and the Intel
When TCO Reboots are not enabled, then the Intel
When TCO Reboots are enabled, then the Intel
the system.
and the SECOND_TO_STS bit (TCO I/O Offset 06h, bit 1) is set, and the DOACPU_STS
bit (TCO I/O Offset 06h, bit 2), the Intel
message by setting the CPU Missing bit in the message.
When the NO-REBOOT bit is not set (reboots intended), and the SECOND_TO_STS bit is
set, the Intel
SECOND_TO_STS bit will still be set. When the processor fails to fetch the first
instruction, the DOA_CPU_STS bit is set, and when the TCO timer times out (actually
for the third time, the first 2 times caused the SECOND_TO_STS bit to be set), the
Intel
Under some conditions, the OS may lock up. To handle this, the TCO Timer is used with
the following algorithm:
1. BIOS programs the TCO Timer, through the TCO_TMR register, with an initial value.
2. An OS-based software agent periodically writes to the TCO_RLD register to reload
3. When the timer reaches 0, an SMI# may be generated. This should only occur
4. Upon generating the SMI#, the TCO Timer automatically reloads with the value in
5. The SMI handler may then:
•
•
The SMLink will still send out the first 8 bits of the message. After the eighth bit,
the logic will stall because there is no integrated LAN controller to send the ACK.
The logic will abort the transfer. External logic may monitor the toggling and use
that to drive LED.
If an LAN controller is connected: send the appropriate message to the LAN
controller.
Generally, this will probably be set to four seconds, but could be greater.
the timer and keep it from generating the SMI#. The software agent may read the
TCO_RLD register to see when it is close to timing out, and possibly determine if
the time-out should be increased.
when the OS was not able to reload the timer. It is assumed that the OS will not be
able to reload the timer if it has locked up.
the TCO_TMR register and start counting down.
®
a. Read the TIMEOUT bit in the TCO_STS register to check that the SMI# was
6300ESB ICH will set the CPU MISSING EVENT bit for the TCO message.
caused by the TCO timer.
®
®
6300ESB ICH will assert PXPCIRST#.
6300ESB ICH will attempt to reboot. After the reboot, the
®
6300ESB ICH will indicate this in the TCO
®
6300ESB ICH will either:
®
6300ESB ICH will attempt to reboot
Order Number: 300641-004US
Intel
®
6300ESB ICH—5
November 2007