NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 68

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

3.10
Table 12.
Intel
DS
68
®
6300ESB I/O Controller Hub
Power Management Interface
Power Management Interface Signals (Sheet 1 of 2)
NOTE: These signals are all in the RESUME well, except THRM# which is in the core well;
SYS_RESET
THRMTRIP
PWRBTN#
RSMRST#
SLP_S3#
SLP_S4#
SLP_S5#
PWROK
THRM#
Name
RI#
#
#
PWROK and RSMRST# which are in the RTC well.
Type
O
O
O
I
I
I
I
I
I
I
Thermal Alarm: Active low signal generated by external hardware to
start the Hardware clock throttling mode. May also generate an SMI#
or SCI.
Thermal Trip: When low, indicates that a thermal trip from the
processor occurred, and corrective action will be taken. This input
buffer has the same characteristics as the FERR# input buffer.
S3 Sleep Control: Power plane control. Shuts off power to all non-
critical systems when in the S3 (Suspend To RAM) state.
S4 Sleep Control: Power plane control. Shuts power to non-critical
systems when in the S4 (Suspend to Disk) or S5 (Soft Off) state.
S5 Sleep Control: Power plane control.
The signal is used to shut power off to all non-critical systems when in
the S5 (Soft Off) state.
Power OK: When asserted, PWROK is an indication to the Intel
6300ESB ICH that core power and PCICLK have been stable for at
least 1 ms. PWROK may be driven asynchronously. When PWROK is
low, the Intel
Traditional designs have a reset button logically ORed with the PWROK
signal from the power supply and the processor’s voltage regulator
module. When this is done with the Intel
PWROK_FLR bit will be set. The Intel
internally as though the RSMRST# signal had gone active. However, it
is not treated as a full power failure. When PWROK goes inactive and
then active (but RSMRST# stays high), the Intel
reboot (regardless of the state of the AFTERG3 bit). When RSMRST#
also goes low before PWROK goes high, then this is a full power failure
and the reboot policy is controlled by the AFTERG3 bit. PWROK must
deassert for a minimum of 100 µseconds (simulation and analysis
shows 3 RTC clock periods are required) in order to fully reset the core
power well and properly generate the PXPCIRST# output.
Power Button: The Power Button will cause SMI# or SCI to indicate a
system request to go to a sleep state. When the system is already in a
sleep state, this signal will cause a wake event. When PWRBTN# is
pressed for more than 4 seconds, this will cause an unconditional
transition (power button override) to the S5 state with only the
PWRBTN# available as a wake event. Override will occur even when
the system is in the S1-S4 states. This signal has an internal pull-up
resistor.
Ring Indicate: From the modem interface. May be enabled as a wake
event, and this is preserved across power failures.
System Reset: This pin forces an internal reset after being
debounced.
Resume Well Reset: Used for resetting the resume power plane
logic. An external RC circuit is required to ensure that the resume well
power is valid prior to RSMRST# going high.
®
6300ESB ICH asserts PXPCIRST#.
Description
®
6300ESB ICH treats this
®
6300ESB ICH, the
Order Number: 300641-004US
®
Intel
6300ESB ICH will
®
6300ESB ICH—3
November 2007
®