NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 764

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

Intel
DS
764
Bits
Default Value:
11
10
9
8
®
Table 699. Offset E0h - E3h: BFCS—BIST FIS Control/Status Register (SATA–
6300ESB I/O Controller Hub
Device:
Offset:
Port 1 BIST FIS Initiate
Port 0 BIST FIS Initiate
BIST FIS Failed (BFF)
BIST FIS Successful
D31:F2)
(Sheet 2 of 3)
(P1BFI)
(P0BFI)
31
E0h–E3h
00000000h
Name
(BFS)
0 = Software clears this bit by writing a ’1’ to it.
1 = This bit is set any time a BIST FIS transmitted by the
NOTE: This bit must be cleared by software prior to initiating
0 = Software clears this bit by writing a ’1’ to it.
1 = This bit is set any time a BIST FIS transmitted by the
NOTE: This bit must be cleared by software prior to initiating
When a rising edge is detected on this bit field, the Intel
6300ESB ICH initiates a BIST FIS to the device on Port 1,
using the parameters specified in this register and the data
specified in BFTD1 and BFTD2. The BIST FIS will only be
initiated if a device on Port 1 is present and ready (not
partial/slumber state). After a BIST FIS is successfully
completed, software must disable and re-enable the port
using the PxE bits at offset 92h prior to attempting additional
BIST FISes or to return the Intel
operational mode. If the BIST FIS fails to complete, as
indicated by the BFF bit in the register, then software can
clear then set the P1BFI bit to initiate another BIST FIS. This
can be retried until the BIST FIS eventually completes
successfully.
When a rising edge is detected on this bit field, the Intel
6300ESB ICH initiates a BIST FIS to the device on Port 0,
using the parameters specified in this register and the data
specified in BFTD1 and BFTD2. The BIST FIS will only be
initiated if a device on Port 0 is present and ready (not
partial/slumber state). After a BIST FIS is successfully
completed, software must disable and re-enable the port
using the PxE bits at offset 92h prior to attempting additional
BIST FISes or to return the Intel
operational mode. If the BIST FIS fails to complete, as
indicated by the BFF bit in the register, then software can
clear then set the P0BFI bit to initiate another BIST FIS. This
can be retried until the BIST FIS eventually completes
successfully.
Intel
from the device.
Intel
status from the device.
a BIST FIS.
a BIST FIS.
®
®
6300ESB ICH receives an R_OK completion status
6300ESB ICH receives an R_ERR completion
Description
Attribute:
Function:
Size:
®
®
6300ESB ICH to a normal
6300ESB ICH to a normal
2
Read/Write, Read/Write Clear
32-bit
Order Number: 300641-004US
Intel
®
®
®
6300ESB ICH—20
November 2007
Access
R/WC
R/WC
R/W
R/W