NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 157

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

5—Intel
Table 70.
5.11.7.4 Sx-G3-Sx, Handling Power Failures
November 2007
Order Number: 300641-004US
®
6300ESB ICH
Causes of Wake Events (Sheet 2 of 2)
In desktop systems, power failures may occur when the AC power is cut (a real power
failure) or when the system is unplugged. In either case, PWROK and RSMRST# are
assumed to go low. Depending on when the power failure occurs and how the system is
designed, different transitions could occur due to a power failure.
The AFTER_G3 bit provides the ability to program whether or not the system should
boot once power returns after a power loss event. When the policy is to not boot, the
system will remain in an S5 state (unless previously in S4). There are only three
possible events that will wake the system after a power failure.
The Intel
failures. When PWROK goes low, the PWROK_FLR bit is set. When RSMRST# goes low,
PWR_FLR is set.
Power Button
GPI[0:n]
USB
RI#
AC’97
Secondary PME#
SMBALERT#
SMBus Slave
Message
PME_B0 (internal
USB EHCI controller)
NOTE: When in the S5 state due to a powerbutton override, the only wake events are Power
NOTE: PME#, RTC, GPI[0:n], and RI# will be wake events from S5 only when it was entered
1. PWRBTN#: PWRBTN# is always enabled as a wake event. When RSMRST# is low
2. RI#: RI# does not have an internal pull-up. Therefore, when this signal is enabled
3. RTC Alarm: The RTC_EN bit is in the RTC well and is preserved after a power loss.
(G3 state), the PWRBTN_STS bit is reset. When the Intel
after power returns (RSMRST# goes high), the PWRBTN# signal is already high
(because V
PWRBTN_STS bit is 0.
as a wake event, it is important to keep this signal powered during the power loss
event. When this signal goes low (active), when power returns the RI_STS bit will
be set and the system will interpret that as a wake event.
Like PWRBTN_STS the RTC_STS bit is cleared when RSMRST# goes low.
Cause
Button, Wake SMBUs Slave Message (01h), and Hard Reset SMBus Slave Messages (03h,
04h).
through software setting the SLP_EN and SLP_TYP bits, or if there is a power failure.
®
6300ESB ICH monitors both PWROK and RSMRST# to detect for power
CC
-standby goes high before RSMRST# goes high) and the
States Can Wake
S1
S1
S1
S1
S1
S1
S1
S1
S1
From
–
–
–
–
–
–
–
–
–
S5
S5
S5
S5
S5
S5
S4
S5
S5
Always enabled as Wake event
GPE0_EN register (after having gone to S5 through
SLP_EN, but not after a power failure.)
NOTE: GPIs that are in the core well are not capable
Set USB1_EN, USB 2_EN and USB3_EN bits in
GPE0_EN Register
Set RI_EN bit in GPE0_EN Register
Set AC’97_EN bit in GPE0_EN Register
Set PME_EN bit in GPE0_EN Register.
SMB_WAK_EN in the GPE0 Register. Always enabled
as Wake event
Wake/SMI# command always enabled as a Wake
Event.
NOTE: SMBus Slave Message may wake the system
Set PME_B0_EN bit in GPE0_EN Register.
of waking the system from sleep states
where the core well is not powered.
from S1-S5, as well as from S5 due to Power
Button Override.
How Enabled
Intel
®
6300ESB ICH exits G3
®
6300ESB I/O Controller Hub
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