NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 601

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

14—Intel
14.2.9
November 2007
Order Number: 300641-004US
Bits
Default Value:
I/O Address:
2
1
0
Table 525. GLOB_CNT—Global Control Register (Sheet 2 of 2)
Lockable:
Note: On reads from a codec, the controller will give the codec a maximum of four frames to
Device:
®
GPI Interrupt Enable
6300ESB ICH
AC’97 Warm Reset
AC’97 Cold Reset#
GLOB_STA—Global Status Register
respond, after which, if no response is received, it will return a dummy read completion
to the processor (with all ‘F’s on the data) and also set the Read Completion Status bit
in the Global Status Register.
Reads across dWord boundaries are not supported.
29
MBAR + 3Ch
00000000h
No
Name
(GIE)
0 = Normal operation.
1 = Writing a ‘1’ to this bit causes a warm reset to occur on
0 = Writing a ‘0’ to this bit causes a cold reset to occur
1 = This bit defaults to ’0’ and hence after reset, the driver
NOTE: This bit is in the Core well.
This bit controls whether the change in status of any GPI
causes an interrupt.
0 = Bit ’0’ of the Global Status Register is set, but no
1 = The change on value of a GPI causes an interrupt and
the AC-link. The warm reset will awaken a suspended
codec without clearing its internal registers. When
software attempts to perform a warm reset while bit_clk
is running, the write will be ignored and the bit will not
change. This bit is self-clearing; it remains set until the
reset completes and bit_clk is seen on the ACLink, after
which it clears itself.
throughout the AC ‘97 circuitry. All data in the controller
and the codec will be lost. Software must clear this bit no
sooner than the minimum number of ms have elapsed.
needs to set this bit to a ‘1’. The value of this bit is
retained after suspends; hence, when this bit is set to a
’1’ prior to suspending, a cold reset is not generated
automatically upon resuming.
interrupt is generated.
sets bit ’0’ of the Global Status Register.
Power Well:
Description
Attribute:
Function:
Size:
5
Read/Write
32-bit
Core
Intel
®
6300ESB I/O Controller Hub
(special)
Access
R/W
R/W
R/W
601
DS