NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 137

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

5—Intel
5.8.3
Table 56.
5.8.4
5.8.5
Table 57.
November 2007
Order Number: 300641-004US
®
6300ESB ICH
Stop Frame
After all data frames, a Stop Frame is driven by the Intel
signal is driven low by the Intel
clocks is determined by the SERIRQ configuration register. The number of clocks
determines the next mode:
Stop Frame Explanation
Specific Interrupts Not Supported via SERIRQ
There are three interrupts seen through the serial stream which are not supported by
the Intel
sharable with other devices within the system. These interrupts are:
The Intel
and will not adjust their level based on the level seen in the serial stream. In addition,
the interrupts IRQ14 and IRQ15 from the serial stream are treated differently than
their ISA counterparts. These two frames are not passed to the Bus Master IDE logic.
The Bus Master IDE logic expects IDE to be behind the Intel
Data Frame Format
Table 57
from the Intel
interrupt may be signaled through both the PCI interrupt input signal and through the
SERIRQ signal (they are shared).
Data Frame Format (Sheet 1 of 2)
•
•
•
Stop Frame Width
Frame
Data
IRQ0. Heartbeat interrupt generated off of the internal 8254 counter 0.
IRQ8#. RTC interrupt may only be generated internally.
IRQ13. Floating point error interrupt generated off of the processor assertion of
FERR#.
#
1
2
3
4
5
6
7
8
2 PCI clocks
3 PCI clocks
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®
shows the format of the data frames. For the PCI interrupts (A-D), the output
6300ESB ICH. These interrupts are generated internally, and are not
6300ESB ICH will ignore the state of these interrupts in the serial stream,
Interrupt
SMI#
®
IRQ0
IRQ1
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
6300ESB ICH is ANDed with the PCI input signal. This way, the
Quiet Mode. Any SERIRQ device may initiate a Start Frame
Continuous Mode. Only the host (Intel
Start Frame
Clocks Past
Frame
Start
11
14
17
20
23
2
5
8
®
6300ESB ICH for 2 or 3 PCI clocks. The number of
Ignored. IRQ0 may only be generated through the
internal 8524.
Before Port 60h latch
Causes SMI# when low. Will set the SERIRQ_SMI_STS
bit, (bit 15).
Next Mode
Comment
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®
6300ESB ICH. The SERIRQ
6300ESB ICH) may initiate a
Intel
®
6300ESB ICH.
®
6300ESB I/O Controller Hub
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