NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 351

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

8—Intel
8.2.5
Table 224. DMASTA—DMA Status Register
November 2007
Order Number: 300641-004US
Bits
Default Value:
7:4
3:0
I/O Address:
Lockable:
®
Device:
Channel Request Status
Channel Terminal Count
6300ESB ICH
DMASTA—DMA Status Register
31
Ch. #0-3 = 08h
Ch. #4-7 = D0h
Undefined
No
Name
Status
When a valid DMA request is pending for a channel, the
corresponding bit is set to 1. When a DMA request is not
pending for a particular channel, the corresponding bit is set
to 0. The source of the DREQ may be hardware or a software
request. Note that channel 4 is the cascade channel, so the
request status of channel 4 is a logical OR of the request
status for channels 0 through 3.
4 = Channel 0
5 = Channel 1 (5)
6 = Channel 2 (6)
7 = Channel 3 (7)
When a channel reaches terminal count (TC), its status bit is
set to 1. When TC has not been reached, the status bit is set
to 0. Channel 4 is programmed for cascade, so the TC bit
response for channel 4 is irrelevant:
0 = Channel 0
1 = Channel 1 (5)
2 = Channel 2 (6)
3 = Channel 3 (7)
Power Well:
Description
Attribute:
Function:
Size:
0
Read-Only
8-bit
Core
Intel
®
6300ESB I/O Controller Hub
Access
RO
RO
351
DS