NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 119

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

5—Intel
5.6.4.9
5.6.4.10 Automatic End of Interrupt Mode
5.6.5
5.6.5.1
5.6.5.2
5.6.6
November 2007
Order Number: 300641-004US
®
6300ESB ICH
Normal End of Interrupt
In Normal EOI, software writes an EOI command before leaving the interrupt service
routine to mark the interrupt as completed. There are two forms of EOI commands:
Specific and Non-Specific. When a Non-Specific EOI command is issued, the PIC will
clear the highest ISR bit of those that are set to one. Non-Specific EOI is the normal
mode of operation of the PIC within the Intel
serviced currently is the interrupt entered with the interrupt acknowledge. When the
PIC is operated in modes which preserve the fully nested structure, software may
determine which ISR bit to clear by issuing a Specific EOI. An ISR bit that is masked
will not be cleared by a Non-Specific EOI when the PIC is in the special mask mode. An
EOI command must be issued for both the master and slave controller.
In this mode, the PIC will automatically perform a Non-Specific EOI operation at the
trailing edge of the last interrupt acknowledge pulse. From a system standpoint, this
mode should be used only when a nested multi-level interrupt structure is not required
within a single PIC. The AEOI mode may only be used in the master controller and not
the slave controller.
Masking Interrupts
Masking on an Individual Interrupt Request
Each interrupt request may be masked individually by the Interrupt Mask Register
(IMR). This register is programmed through OCW1. Each bit in the IMR masks one
interrupt channel. Masking IRQ2 on the master controller will mask all requests for
service from the slave controller.
Special Mask Mode
Some applications may require an interrupt service routine to dynamically alter the
system priority structure during its execution under software control. For example, the
routine may wish to inhibit lower priority requests for a portion of its execution but
enable some of them for another portion.
The special mask mode enables all interrupts not masked by a bit set in the Mask
Register. Normally, when an interrupt service routine acknowledges an interrupt
without issuing an EOI to clear the ISR bit, the interrupt controller inhibits all lower
priority requests. In the special mask mode, any interrupts may be selectively enabled
by loading the Mask Register with the appropriate pattern. The special mask mode is
set by OCW3 where: SSMM=1, SMM=1, and cleared where SSMM=1, SMM=0.
Steering PCI Interrupts
The Intel
internally routed to interrupts 3-7, 9-12, 14 or 15. The assignment is programmable
through the PIRQx Route Control registers, located at 60-63h and 68-6Bh in function 0.
One or more PIRQx# lines may be routed to the same IRQx input. When interrupt
steering is not required, the Route Registers may be programmed to disable steering.
The PIRQx# lines are defined as active low, level sensitive to allow multiple interrupts
on a PCI Board to share a single line across the connector. When a PIRQx# is routed to
specified IRQ line, software must change the IRQ's corresponding ELCR bit to level
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6300ESB ICH may be programmed to allow PIRQA#-PIRQH# to be
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6300ESB ICH, as the interrupt being
Intel
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6300ESB I/O Controller Hub
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