NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 76
NHE6300ESB S L7XJ
Manufacturer Part Number
NHE6300ESB S L7XJ
Description
Manufacturer
Intel
Datasheet
1.NHE6300ESB_S_L7XJ.pdf
(848 pages)
Specifications of NHE6300ESB S L7XJ
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Table 21.
3.20
Table 22.
Intel
DS
76
®
6300ESB I/O Controller Hub
General Purpose I/O Signals (Sheet 2 of 2)
Power and Ground
Power and Ground Signals (Sheet 1 of 2)
NOTES:
1. GPIO[0:7], GPIO[16:21, 23], and GPIO[32:55] are in the core well.
2. GPIO[8:15] and GPIO[24:31] are in the suspend well.
3. Core-well GPIO are 5 V tolerant, except for GPIO[7:6] and [32:43].
4. Resume-well GPIO are not 5 V tolerant.
5. GPIO[56:57] pads are in the suspend well, the register bits are in the RTC well.
GPIO[40:43]
GPIO[44:55]
GPIO[56:57]
GPIO[58:63]
Signal Name
VCCSUS1_5
V5REF_Sus
VccSus3_3
VCC3_3
VCC1_5
VCCRTC
VCCREF
VCCHI
V5REF
HIREF
Name
VCCA
Type
I/O
I/O
I/O
3.3 V supply for core well I/O buffers. This power may be shut off in S3, S4,
or S5 states.
1.5 V supply for core well logic. This power may be shut off in S3, S4, S5 or
S5 states.
1.5 V supply for Hub Interface 1.5 logic.
This power may be shut off in S3, S4, and S5 states.
Reference for 5 V tolerance on core well inputs. This power may be shut off
in S3, S4, S5 or G3 states.
3.3V reference voltage for PCI-X inputs
1.5V supply for Hub Interface PLL.
This power may be shut off in S3, S4, and S5 states.
Analog Input. Expected voltages are 350 mV for the Hub Interface 1.5
(Enhanced Hub Interface) Parallel Termination.
This power is shut off in S3, S4, S5 and G3 states.
3.3 V supply for resume well I/O buffers. This power is not expected to be
shut off unless the system is unplugged in desktop configurations.
1.5 V supply for resume well logic. This power is not expected to be shut off
unless the system is unplugged in desktop configurations.
Reference for 5 V tolerance on resume well inputs. This power is not
expected to be shut off unless the system is unplugged in desktop
configurations.
3.3 V (may drop to 2.0 V min. in G3 state) supply for the RTC well. This
power is not expected to be shut off unless the RTC battery is removed or
completely drained.
NOTE: Implementations should not attempt to clear CMOS by using a
OD
May be input or output. Core power well.
NOTE: These GPIOs have High Strength Output Capability (for
Reserved. These GPIO are not implemented.
Output only. Resume and RTC power wells. Unmuxed.
Reserved. These GPIO are not implemented.
jumper to pull VccRTC low. Clearing CMOS in an Intel
ICH-based platform may be done by using a jumper on RTCRST# or
GPI, or using SAFEMODE strap.
driving LEDs).
Description
Description
Order Number: 300641-004US
Intel
®
6300ESB ICH—3
®
November 2007
6300ESB
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