NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 318

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

Table 191. Offset 44h: ACPI_CNTL—ACPI Control (LPC I/F—D31:F0) (Sheet 2 of
Intel
DS
318
Bits
Default Value:
2:0
4
3
®
6300ESB I/O Controller Hub
Lockable:
Device:
Offset:
SCI_IRQ_SEL: SCI IRQ
ACPI_EN: ACPI Enable
2)
Reserved
31
44h
00h
No
Name
Select
0 = Disable.
1 = Decode of the I/O range pointed to by the ACPI base
Reserved.
Specifies on which IRQ the SCI will internally appear. When
not using the APIC, the SCI must be routed to IRQ9-11, and
that interrupt is not shared with the SERIRQ stream, but may
be shared with other PCI interrupts. When using the APIC,
the SCI may also be mapped to IRQ20-23, and may be
shared with other interrupts.
Bits
000
001
010
011
100
101
110
111
NOTE: When the interrupt is mapped to APIC interrupts 9,
register is enabled, and the ACPI power management
function is enabled. Note that the APM power
management ranges (B2/B3h) are always enabled and
are not affected by this bit.
10, or 11, the APIC should be programmed for active-
high reception. When the interrupt is mapped to APIC
interrupts 20 through 23, the APIC should be
programmed for active-low reception.
SCI Map
IRQ9
IRQ10
IRQ11
Reserved
IRQ20 (Only available when APIC enabled)
IRQ21 (Only available when APIC enabled)
IRQ22 (Only available when APIC enabled)
IRQ23 (Only available when APIC enabled)
Power Well:
Description
Attribute:
Function:
Size:
0
Read/Write
8-bit
Core
Order Number: 300641-004US
Intel
®
6300ESB ICH—8
November 2007
Access
R/W
R/W