NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 668

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

Intel
DS
668
15:1
Bits
12
11
10
09
08
07
1
®
Table 604. Offset 3E: BCTRL—Bridge Control (Sheet 1 of 3)
6300ESB I/O Controller Hub
Secondary
Device
Fast Back-
PERR# to
Offset
Reserved
Primary
to-Back
Discard
Discard
Discard
Discard
SERR#
SERR#
(DTSE)
(DTSb)
Name
Enable
Enable
Status
Enable
(SDT)
Timer
Timer
Timer
Timer
(PDT)
(FBE)
28
3E
Reserved.
When this bit is set to ‘1’, PCI-X PERR NMI reporting is
enabled. In addition to setting this bit, you also must set bit
’1’ of D30_F0 PNE Register.
When this bit is set to a ‘1’ and PERR# is asserted on PCI-X,
the PERR# Assertion detect status bit in the Secondary
Status Register will indicate a PERR# internal SERR#
assertion. The SERR# can be a s source on NMI.
Controls the generation of SERR# on the primary interface in
response to a timer discard on the secondary interface.
When 0: Do not generate SERR# on a secondary timer
discard
When 1: Generate SERR# in response to a secondary timer
discard
This bit is set to a ’1’ when the secondary discard timer
expires (there is no discard timer for the primary interface).
Sets the maximum number of PCI clock cycles that the Intel
6300ESB ICH waits for an initiator on PCI to repeat a delayed
transaction request. The counter starts once the delayed
transaction completion is at the head of the queue. If the
master has not repeated the transaction at least once before
the counter expires, the Intel
transaction from its queues.
When 0: The PCI master timeout value is between 2^15 and
2^16 PCI clocks.
When 1: The PCI master timeout value is between 2^10 and
2^11 PCI clocks
Not relevant to Hub Interface. This bit is R/W for software
compatibility only.
The Intel
cycles on the PCI-X bus from Hub Interface initiated
transactions.
®
6300ESB ICH cannot generate fast back-to-back
Description
Section 7.1.28
®
6300ESB ICH discards the
Attribute:
Function
Size:
0
Read/Write
16-bit
®
Order Number: 300641-004US
Reset
Value
Intel
0h
0
0
0
0
0
®
6300ESB ICH—18
November 2007
Access
R/WC
R/W
R/W
R/W
RO
RO