NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 571

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

13—Intel
13.2.5
13.2.6
November 2007
Order Number: 300641-004US
15:0
Bits
Bits
Default Value:
Default Value:
7:5
4:0
I/O Address:
I/O Address:
Table 489. x_PICB—Position In Current Buffer Register
Table 490. x_PIV—Prefetched Index Value Register
Lockable:
Lockable:
Note: Software may read the registers at offsets 08h, 0Ah, and 0Bh by performing a 32-bit
Device:
Device:
®
6300ESB ICH
Position In Current
Prefetched Index
Buffer[15:0]
Value[4:0]
x_PICB—Position In Current Buffer Register
x_PIV—Prefetched Index Value Register
read from address offset 08h. Software may also read this register individually by doing
a single 8-bit read to offset 0Ah. Reads across dWord boundaries are not supported.
31
NABMBAR + 08h (PIPICB), NABMBAR +
18h (POPICB), NABMBAR + 28h
(MCPICB), MBBAR + 48h (MC2PICB),
MBBAR + 58h (PI2PICB), MBBAR + 68h
(SPPICB)
0000h
No
Name
31
NABMBAR + 0Ah (PIPIV), NABMBAR + 1Ah
(POPIV), NABMBAR + 2Ah (MCPIV),
MBBAR + 4Ah (MC2PIV), MBBAR + 5Ah
(PI2PIV), MBBAR + 6Ah (SPPIV)
00h
No
Name
These bits represent the number of samples left to be
processed in the current buffer. This means the number of
samples not yet read from memory (in the case of reads from
memory) or not yet written to memory (in the case of writes
to memory) irrespective of the number of samples that have
been transmitted/received across AC-link.
Hardwired to 0.
These bits represent which buffer descriptor in the list has
been prefetched. The bits in this register are also modulo 32
and roll over after they reach 31.
Description
Description
Power Well:
Power Well:
Attribute:
Attribute:
Function:
Function:
Size:
Size:
5
Read-Only
16-bit
Core
5
Read-Only
8-bit
Core
Intel
®
6300ESB I/O Controller Hub
Access
Access
RO
RO
571
DS