NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 215

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

5—Intel
November 2007
Order Number: 300641-004US
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6300ESB ICH
A transfer set is a collection of data which requires more than one USB transaction to
completely move the data across the USB interface. An example might be a large print
file which requires numerous TDs in multiple frames to completely transfer the data.
Reception of a data packet that is less than the endpoint’s Max Packet size during
Control, Bulk or Interrupt transfers signals the completion of the transfer set, even
when there are active TDs remaining for this transfer set. Setting the SPD bit in a TD
indicates to the HC to set the USB Interrupt bit in the HC status register at the end of
the frame in which this event occurs. This feature streamlines the processing of input
on these transfer types. When the Short Packet Interrupt Enable bit in the Interrupt
Enable register is set, a hardware interrupt is signaled to the system at the end of the
frame where the event occurred.
Serial Bus Babble
When a device transmits on the USB for a time greater than its assigned Max Length, it
is said to be babbling. Since isochrony may be destroyed by a babbling device, this
error results in the Active bit in the TD being cleared to 0 and the Stalled and Babble
bits being set to one. The C_ERR field is not decremented for a babble. The USB Error
Interrupt bit in the HC Status register is set to 1 at the end of the frame. A hardware
interrupt is signaled to the system.
When an EOF babble was caused by the Intel
for instance), the Intel
the start of the next frame.
Stalled
This event indicates that a device/endpoint returned a STALL handshake during a
transaction or that the transaction ended in an error condition. The TDs Stalled bit is
set and the Active bit is cleared. Reception of a STALL does not decrement the error
counter. A hardware interrupt is signaled to the system.
Data Buffer Error
This event indicates that an overrun of incoming data or a under-run of outgoing data
has occurred for this transaction. This would generally be caused by the Intel
6300ESB ICH not being able to access required data buffers in memory within
necessary latency requirements. Either of these conditions will cause the C_ERR field of
the TD to be decremented.
When C_ERR decrements to zero, the Active bit in the TD is cleared, the Stalled bit is
set, the USB Error Interrupt bit in the HC Status register is set to 1 at the end of the
frame and a hardware interrupt is signaled to the system.
Bit Stuff Error
A bit stuff error results from the detection of a sequence of more that 6 ones in a row
within the incoming data stream. This will cause the C_ERR field of the TD to be
decremented. When the C_ERR field decrements to 0, the Active bit in the TD is cleared
to 0, the Stalled bit is set to one, the USB Error Interrupt bit in the HC Status register is
set to 1 at the end of the frame and a hardware interrupt is signaled to the system.
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6300ESB ICH will force a bit stuff error followed by an EOP and
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6300ESB ICH (due to incorrect schedule
Intel
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6300ESB I/O Controller Hub
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