NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 294

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

Table 159. Offset 1Bh: SMLT—Secondary Master Latency Timer Register (HUB-
7.1.14
Table 160. Offset 1Ch: IOBASE—I/O Base Register (HUB-PCI—D30:F0)
Intel
DS
294
Bits
Bits
Default Value:
Default Value:
7:3
2:0
7:4
3:0
®
6300ESB I/O Controller Hub
Device:
Device:
Offset:
Offset:
I/O Address Base bits
Master Latency Count
I/O Addressing
Capability
A value of 00h disables the timer such that the North PCI initiator logic is never forced
to end a burst prematurely due to a timeout.
PCI—D30:F0)
Offset 1Ch: IOBASE—I/O Base Register (HUB-
PCI—D30:F0)
Reserved
[15:12]
30
1Bh
00h
Name
30
1Ch
F0h
Name
5-bit value that indicates the number of PCI clocks, in 8-clock
increments, that the Intel
master of the bus.
Reserved.
I/O Base bits corresponding to address lines 15:12 for 4-
Kbyte alignment. Bits 11:0 are assumed to be padded to
000h.
This is hardwired to 0h, indicating that the Hub Interface to
PCI bridge does not support 32-bit I/O addressing. This
means that the I/O base and limit upper address registers
must be read only.
Description
Description
®
Attribute:
Attribute:
Function:
Function:
6300ESB ICH will remain as
Size:
Size:
0
Read/Write
8-bit
0
Read/Write
8-bit
Order Number: 300641-004US
Intel
®
6300ESB ICH—7
November 2007
Access
Access
R/W
R/W
RO