NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 569

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

13—Intel
13.2.3
13.2.4
November 2007
Order Number: 300641-004US
Bits
Bits
Default Value:
Default Value:
7:5
4:0
7:5
4:0
I/O Address:
I/O Address:
Table 486. x_CIV—Current Index Value Register
Table 487. x_LVI—Last Valid Index Register
Lockable:
Lockable:
Note: Software may read the registers at offsets 04h, 05h and 06h simultaneously by
Device:
Device:
®
Last Valid Index[4:0]
6300ESB ICH
Current Index
Value[4:0]
x_LVI—Last Valid Index Register
x_SR—Status Register
performing a single 32-bit read from address offset 04h. Software may also read this
register individually by doing a single 8-bit read to offset 05h. Reads across dWord
boundaries are not supported.
31
NABMBAR + 04h (PICIV), NABMBAR + 04h
(PICIV), NABMBAR + 04h (PICIV), MBBAR
+ 44h (MC2CIV), MBBAR + 54h (PI2CIV),
MBBAR + 64h (SPCIV)
00h
No
Name
31
NABMBAR + 05h (PILVI), NABMBAR + 15h
(POLVI), NABMBAR + 15h (POLVI),
NABMBAR + 15h (POLVI), MBBAR + 55h
(PI2LVI), MBBAR + 65h (SPLVI)
00h
No
Name
Hardwired to ‘0’.
These bits represent which buffer descriptor within the list of
32 descriptors is currently being processed. As each
descriptor is processed, this value is incremented. The value
rolls over after it reaches 31.
Hardwired to ‘0’.
This value represents the last valid descriptor in the list. This
value is updated by the software each time it prepares a new
buffer and adds it to the list.
Description
Description
Power Well:
Power Well:
Attribute:
Attribute:
Function:
Function:
Size:
Size:
5
Read-Only
8-bit
Core
5
Read/Write
8-bit
Core
Intel
®
6300ESB I/O Controller Hub
Access
Access
R/W
RO
569
DS