NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 290

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

7.1.4
Table 150. Offset 06 - 07h: PD_STS—Primary Device Status Register (HUB-PCI—
Intel
DS
290
10:9
Bits
Default Value:
4:0
15
14
13
12
11
8
7
6
5
®
6300ESB I/O Controller Hub
Note: For the writable bits in this register, writing a 1 will clear the bit. Writing a 0 to the bit
Device:
Master Data Parity Error
DEVSEL# Timing Status
User Definable Features
Offset:
Signaled System Error
Received Master Abort
Received Target Abort
Signaled Target Abort
Detected Parity Error
Fast Back to Back
Detected (MDPD)
66 MHz Capable
Offset 06 - 07h: PD_STS—Primary Device Status
Register (HUB-PCI—D30:F0)
will have no effect.
D30:F0)
Reserved
30
06-07h
0080h
Name
(RMA)
(UDF)
(DPE)
(SSE)
(RTA)
(STA)
0 = Software clears this bit by writing a ‘1’ to the bit location.
1 = Indicates that the Intel
0 = Software clears this bit by writing a ‘1’ to the bit location.
1 = An address, or command parity error, or special cycles
0 = Software clears this bit by writing a ‘1’ to the bit location.
1 = The Intel
0 = Software clears this bit by writing a ‘1’ to the bit location.
1 = The Intel
0 = Software clears this bit by writing a ‘1’ to the bit location.
1 = The Intel
00h = Fast timing. This register applies to the Hub Interface.
Since this register applies to the Hub Interface, the Intel
6300ESB ICH must interpret this bit differently than it is in
the PCI spec.
0 = Software clears this bit by writing a ‘1’ to the bit location.
1 = The Intel
Hardwired to ‘1’.
Hardwired to ‘0’.
Hardwired to ‘0’.
Reserved.
error on the Hub Interface and the Hub Interface Parity
Unsupported bit is cleared (D30:F0:40h:bit20). This bit
gets set even when the Parity Error Response bit (offset
04, bit 6) is not set.
data parity error has been detected on the PCI bus, and
the Parity Error Response bit (D30:F0, Offset 04h, bit 6)
is set. When this bit is set because of parity error and the
D30:F0 SERR_EN bit (Offset 04h, bit 8) is also set, the
Intel
routed to SMI#).
the Hub Interface device.
Hub Interface device. The setting of this bit can be
enabled to cause an internal SERR#.
on the Hub Interface.
Hub Interface and the Parity Error Response bit in the
Command Register (offset 04h, bit 6) is set.
®
6300ESB ICH will generate an NMI (or SMI# if NMI
®
®
®
®
6300ESB ICH received a target abort from the
6300ESB ICH received a master abort from
6300ESB ICH signals a target abort condition
6300ESB ICH detects a parity error on the
Description
Attribute:
Function:
®
6300ESB ICH detected a parity
Size:
0
Read/Write Clear
16-bit
Order Number: 300641-004US
Intel
®
®
6300ESB ICH—7
November 2007
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