NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 746

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

20.1.13 Offset 20h - 23h: BAR—Legacy Bus Master Base
20.1.14 Offset 2Ch - 2Dh: SVID—Subsystem Vendor ID
Intel
DS
746
31:1
15:4
15:0
Bits
Bits
Default Value:
Default Value:
3:1
6
0
®
Table 673. Offset 20h - 23h: BAR—Legacy Bus Master Base Address Register
Table 674. Offset 2Ch - 2Dh: SVID—Subsystem Vendor ID (SATA–D31:F2)
6300ESB I/O Controller Hub
Lockable:
Note: The Bus Master IDE interface function uses Base Address register 5 to request a 16-
Device:
Device:
Resource Type Indicator
Offset:
Offset:
Subsystem Vendor ID
Base Address
Address
Register (SATA–D31:F2)
byte IO space to provide a software interface to the Bus Master functions. Only 12
bytes are actually used (6 bytes for primary, 6 bytes for secondary). Only bits [15:4]
are used to decode the address.
(SATA–D31:F2)
(SATA–D31:F2)
Reserved
Reserved
(SVID)
31
20h-23h
00000001h
Name
31
2Ch-2Dh
00h
No
Name
(RTE)
Reserved.
Base address of the I/O space (16 consecutive I/O locations).
Reserved.
Hardwired to ’1’, indicating a request for IO space.
The SVID register, in combination with the Subsystem ID
(SID) register, enables the operating system (OS) to
distinguish subsystems from each other. Software (BIOS)
sets the value in this register. After that, the value may be
read, but subsequent writes to this register have no effect.
The value written to this register will also be readable through
the corresponding SVID registers for the USB#1, USB#2 and
SMBus functions.
Power Well:
Description
Description
Attribute:
Attribute:
Function:
Function:
Size:
Size:
2
Read/Write
32-bit
2
Read/Write Once
16-bit
Core
Order Number: 300641-004US
Intel
®
6300ESB ICH—20
November 2007
Access
Access
R/WO
R/W
RO