NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 387

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NHE6300ESB S L7XJ

Manufacturer Part Number
NHE6300ESB S L7XJ
Description
Manufacturer
Intel
Datasheet

Specifications of NHE6300ESB S L7XJ

Lead Free Status / RoHS Status
Compliant
8—Intel
8.8.1.3
Table 274. Offset A4h: GEN_PMCON_3—General PM Configuration 3 Register
November 2007
Order Number: 300641-004US
NOTE: RSMRST# is sampled using the RTC clock. Therefore, low times that are less than one RTC clock period
Bits
Default Value:
7:6
5:3
2
1
0
Lockable:
®
Note: Usage: ACPI or Legacy.
may not be detected by the Intel
Device:
PWR_FLR: Power Failure
Offset:
6300ESB ICH
RTC_PWR_STS: RTC
SWSMI_RATE_SEL
Power Status
AFTERG3_EN
Offset A4h: GEN_PMCON_3—General PM Configuration 3
Register (PM—D31:F0)
(PM—D31:F0)
Reserved
31
A4h
00h
No
Name
This 2-bit value indicates when the SWSMI timer will time out.
Valid values are:
00 1.5 ms ± 0.5 ms
01 16 ms ± 4 ms
10 32 ms ± 4 ms
11 64 ms ± 4 ms
Reserved.
This bit is set when RTCRST# is low. The bit is not cleared by
any type of reset.
This bit is in the RTC well, and is not cleared by any type of
reset except RTCRST#.
0 = Indicates that the trickle current has not failed since the
1 = Indicates that the trickle current (from the main battery
NOTE: Clearing CMOS in a processor-based platform may be
Determines what state to go to when power is re-applied
after a power failure (G3 state). This bit is in the RTC well and
is not cleared by any type of reset except writes to CF9h or
RTCRST#.
0 = System will return to S0 state (boot) after power is re-
1 = System will return to the S5 state (except when it was in
last time the bit was cleared. Software clears this bit by
writing a 1 to the bit position.
or trickle supply) was removed or failed.
applied.
S4, in which case it will return to S4). In the S5 state, the
only enabled wake event is the Power Button or any
enabled wake event that was preserved through the
power failure.
®
done by using a jumper on RTCRST# or GPI, or using
SAFEMODE strap. Implementations should not
attempt to clear CMOS by using a jumper to pull
VccRTC low.
6300ESB ICH.
Power Well:
Description
Attribute:
Function:
Size:
0
Read/Write
8-bit
RTC
Intel
®
6300ESB I/O Controller Hub
Access
R/WC
R/W
R/W
R/W
387
DS

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