NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 133

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

5—Intel
5.7.6.2
5.7.7
5.7.7.1
November 2007
Order Number: 300641-004US
®
Note: PSB Interrupt Delivery compatibility with processor clock control depends on the
6300ESB ICH
Since they are edge triggered, the interrupts that are allocated to the PCI bus for this
scheme may not be shared with any other interrupt (such as the standard PCI
PIRQ[A:D], those received via SERIRQ#, or the internal level-triggered interrupts such
as SCI or TCO).
The Intel
attempt to use IRQ0, 2, 8, or 13.
Registers and Bits Associated with PCI Interrupt Delivery
Capabilities Indication
The capability to support PCI interrupt delivery will be indicated through ACPI
configuration techniques. This involves the BIOS creating a data structure that gets
reported to the ACPI configuration software. The OS reads the PRQ bit in the APIC
Version Register to see when the Intel
based interrupt messages.
Interrupt Message Register
The PCI devices will all write their message into the IRQ Pin Assertion Register, which is
a memory-Mapped register located at the APIC base memory location + 20h.
Processor System Bus Interrupt Delivery
Theory of Operation
For processors that support Processor System Bus interrupt delivery, the Intel
6300ESB ICH has an option to let the integrated I/O APIC behave as an I/O (x) APIC.
In this case, it will deliver interrupt messages to the processor in a parallel manner,
rather than using the I/O APIC serial scheme. The Intel
be compatible with the I/O (x) APIC specification, Rev 1.1
This is done by the Intel
memory location that is snooped by the processor(s). The processor(s) snoop the cycle
to know which interrupt goes active.
The processor enables the mode by setting the I/O APIC Enable (APIC_EN) bit and by
setting the DT bit in the I/O APIC ID register.
The following sequence is used:
processor, not the Intel
1. When the Intel
2. Internally, the Intel
3. The Intel
triggered mode or a change for level-triggered mode), it sets or resets the internal
IRR bit associated with that interrupt.
automatically flushes upstream buffers. This may be internally implemented similar
to a DMA device request.
the appropriate address with the appropriate data. The address and data formats
are described below in
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6300ESB ICH will ignore interrupt messages sent by PCI masters that
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6300ESB ICH then delivers the message by performing a write cycle to
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6300ESB ICH detects an interrupt event (active edge for edge-
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®
®
6300ESB ICH.
6300ESB ICH requests to use the bus in a way that
6300ESB ICH writing (through the Hub Interface) to a
Section 5.7.7.5, “Interrupt Message
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6300ESB ICH is capable of supporting PCI-
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6300ESB ICH is intended to
Intel
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Format”.
6300ESB I/O Controller Hub
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