NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 826

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

Figure 66. Test Mode Entry (XOR Chain Example)
23.2
23.3
Figure 67. Example XOR Chain Circuitry
23.3.1
Intel
DS
826
®
6300ESB I/O Controller Hub
Tri-State Mode
When in the tri-state mode, all outputs and bi-directional pin are tri-stated, including
the XOR Chain outputs.
XOR Chain Mode
In the Intel
testing are implemented with XOR Chains. The Intel
grouped into seven independent XOR chains which are enabled individually. When an
XOR chain is enabled, all output and bi-directional buffers within that chain are tri-
stated, except for the XOR chain output. Every signal in the enabled XOR chain (except
for the XOR chain’s output) functions as an input. All output and bi-directional buffers
for pins not in the selected XOR chain are tri-stated.
of XOR chain circuitry.
XOR Chain Testability Algorithm Example
XOR chain testing allows motherboard manufacturers to check component connectivity
(e.g., opens and shorts to V
Table
Other Signal
RSMRST#
RTSRST#
PWROK
Outputs
732.
®
Vcc
Input
Pin 1
6300ESB ICH, provisions for Automated Test Equipment (ATE) board level
Input
Pin 2
Number of PCI Clocks RTCRST# driven low
CC
after PWROK active
or GND). An example algorithm to do this is shown in
Input
Pin 3
All Output Signals Tri-Stated
Input
Pin 4
after RTCRST# driven high
Number of PCI Clocks
Input
Pin 5
®
Figure 67
6300ESB ICH signals are
Input
Pin 6
is a schematic example
Order Number: 300641-004US
Intel
XOR Chain Output Enabled
Test Mode Entered
®
6300ESB ICH—23
Output
Chain
XOR
November 2007