NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 648

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

18.2
18.2.1
18.2.2
Intel
DS
648
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6300ESB I/O Controller Hub
Note: When the EN1K bit is set in the Intel
and limit registers are changed so that the top six bits of the 8-bit field define bits
[15:10] of the I/O base/limit address, and the bottom two bits read only as 0h to
indicate support for 16-bit I/O addressing. Bits [9:0] are assumed to be ‘0’ for the base
register and ‘1’ for the limit register, which naturally aligns the address to a 1 Kbyte
boundary.
Memory Window Addressing
This section describes the memory windows that may be set up in the bridge. Refer to
Section 18.2.2, “Prefetchable Memory Base and Limit Address Registers, Upper 32-Bit
Registers”
To enable outbound memory transactions, the memory space enable bit in the
command register must be set (bit 1 of offset 04-05h). To enable inbound memory
transactions, the master enable bit in the command register must be set (bit 2 of offset
04-05h). The Intel
6300ESB ICH supports 64 bits of addressing (DAC cycles) on both interfaces.
Memory Base and Limit Address Registers
The memory base address and memory limit address registers define an address range
that the Intel
The Intel
X when the address falls within the range, and forwards it from PCI-X to the Hub
Interface when the address is outside the range, provided that they do not fall into the
prefetchable memory range (see
Address Registers, Upper 32-Bit
addressing only (addresses 4 Gbytes). It has a granularity and alignment of
1 Mbyte.
This range is defined by a 16-bit base address register at offset 20h in configuration
space and a 16-bit limit address register at offset 22h. The top 12 bits of each of these
registers correspond to bits [31:20] of the memory address. The low four bits are
hardwired to ‘0’. The low 20 bits of the base address are assumed to be all ‘0’, which
results in a natural alignment to a 1 Mbyte boundary. The low 20 bits of the limit
address are assumed to be all ‘1’s, which results in an alignment to the top of a 1
Mbyte block.
Setting the base to a value greater than that of the limit turns off the memory range.
Prefetchable Memory Base and Limit Address
Registers, Upper 32-Bit Registers
The prefetchable memory base and address registers, along with their upper 32-bit
counterparts, define an additional address range that the Intel
forward accesses. The Intel
Hub Interface to PCI-X when the address falls within the range, and forwards
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Memory-mapped I/O Base and Limit registers
Prefetchable Memory Base and Limit registers
Prefetchable Memory Base and Limit upper 32 bits register
Memory Enable bit in the Command register
Master Enable bit in the Command register
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to see how memory cycles in the VGA range are handled.
6300ESB ICH forwards a memory transaction from the Hub Interface to PCI-
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6300ESB ICH uses to determine when to forward memory commands.
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6300ESB ICH does not prefetch data from PCI devices. The Intel
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6300ESB ICH forwards a memory transaction from the
Registers”). This memory range supports 32-bit
Section 18.2.2, “Prefetchable Memory Base and Limit
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6300ESB ICH Configuration register, the base
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Order Number: 300641-004US
6300ESB ICH uses to
Intel
®
6300ESB ICH—18
November 2007
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