NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 239

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

5—Intel
5.19.2.1 Command Protocols
Table 115. Quick Protocol
Table 116. Send/Receive Byte Protocol without PEC
November 2007
Order Number: 300641-004US
®
6300ESB ICH
In all of the following commands, the Host Status Register (offset 00h) is used to
determine the progress of the command. While the command is in operation, the
HOST_BUSY bit is set. When the command completes successfully, the INTR bit will be
set in the Host Status Register. When the device does not respond with an
acknowledge, and the transaction times out, the DEV_ERR bit is set. When software
sets the KILL bit in the Host Control Register while the command is running, the
transaction will stop and the FAILED bit will be set. When the KILL bit is set, the Intel
6300ESB ICH will abort current transaction by asserting SMBCLK low for greater than
the timeout period, assert a STOP condition and then releases SMBCLK and SMBDATA.
However, setting the KILL bit does not affect SMLINK or TCO transactions or causes
Intel
Quick Command
When programmed for a Quick Command, the Transmit Slave Address Register is sent.
The PEC byte is never appended to the Quick Protocol. Software should force the
PEC_EN bit to ‘0’ when performing the Quick Command. Software must force the
I2C_EN bit to 0 when running this command. The format of the protocol is shown in
Table
Send Byte/Receive Byte
For the Send Byte command, the Transmit Slave Address and Device Command
Registers are sent
For the Receive Byte command, the Transmit Slave Address Register is sent. The data
received is stored in the DATA0 register. Software must force the I2C_EN bit to 0 when
running this command.
The Receive Byte is similar to a Send Byte, the only difference is the direction of data
transfer. The format of the protocol is shown in
11–18
2–8
Bit
10
19
20
2–8
1
9
®
Bit
10
11
1
9
115.
6300ESB ICH to force a timeout when it is not performing a transaction.
Start
Slave Address - 7 bits
Write
Acknowledge from slave
Command code - 8 bits
Acknowledge from slave
Stop
Send Byte Protocol
Start Condition
Slave Address - 7 bits
Read / Write Direction
Acknowledge from
slave
Stop
Description
Description
11–18
2–8
Bit
10
19
20
Table 116
1
9
Receive Byte Protocol
Start
Slave Address - 7 bits
Read
Acknowledge from slave
Data byte from slave
NOT Acknowledge
Stop
and
Intel
Table
®
Description
6300ESB I/O Controller Hub
117.
239
®
DS