NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 740

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

Intel
DS
740
Bits
Default Value:
3
2
1
0
®
Table 663. Offset 04h - 05h: CMD—Command Register (SATA–D31:F2) (Sheet
6300ESB I/O Controller Hub
IOSE - I/O Space Enable
Device:
Offset:
Memory Space Enable
Special Cycle Enable
Bus Master Enable
2 of 2)
(IOSE)
31
04h-05h
00h
Name
(BME)
(MSE)
(SCE)
Reserved as ‘0’.
Controls the Intel
master for IDE Bus Master transfers. This bit does not impact
the generation of completions for split transaction commands.
The SATA Controller does not contain memory space.
This bit controls access to the I/O space registers.
0 = Disables access to the Legacy or Native IDE ports (both
1 = Enable. Note that the Base Address register for the Bus
Primary and Secondary) as well as the Bus Master IO
registers.
Master registers should be programmed before this bit is
set.
®
6300ESB ICH’s ability to act as a PCI
Description
Attribute:
Function:
Size:
2
Read-Only, Read/Write
16-bit
Order Number: 300641-004US
Intel
®
6300ESB ICH—20
November 2007
Access
R/W
R/W
RO
RO