NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 269

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

5—Intel
5.20.2.23Register Access
Table 140. Output Tag Slot 0
November 2007
Order Number: 300641-004US
®
6300ESB ICH
Reads from 54h/D4h will not be transmitted across the link in slot 1 and 2. The data
from the most recent slot 12 is returned on reads from offset 54h/D4h.
In the Intel
connected to the SDOUT pin. The following mechanism is used to address the primary,
secondary, and tertiary codecs individually.
The primary device uses bit 19 of slot 1 as the direction bit to specify read or write. Bits
[18:12] of slot 1 are used for the register index. For I/O writes to the primary codec,
the valid bits [14:13] for slots 1 and 2 must be set in slot 0, as shown in
1 is used to transmit the register address, and slot 2 is used to transmit data. For I/O
reads to the primary codec, only slot 1 should be valid since only an address is
transmitted. For I/O reads only slot 1 valid bit is set, while for I/O writes both slots 1
and 2 valid bits are set.
The secondary and tertiary codec registers are accessed using slots 1 and 2 as
described above, however the slot valid bits for slots 1 and 2 are marked invalid in slot
0 and the codec ID bits [1:0] (bit 0 and bit 1 of slot 0) is set to a non zero value. This
allows the secondary or tertiary codec to monitor the slot valid bits of slots 1 and 2, and
bits [1:0] of slot 0 to determine when the access is directed to the secondary or tertiary
codec. When the register access is targeted to the secondary or tertiary codec, slot 1
and 2 will contain the address and data for the register access. Since slots 1 and 2 are
marked invalid, the primary codec will ignore these accesses.
When accessing the codec registers, only one I/O cycle may be pending across the AC-
link at any time. The Intel
across the AC-link (i.e., writes across the link are indicated as complete before they are
actually sent across the link). In order to prevent a second I/O write from occurring
before the first one is complete, software must monitor the CAS bit in the Codec Access
Semaphore register which indicates that a codec access is pending. Once the CAS bit is
cleared, then another codec access (read or write) may go through. The exception to
this being reads to offset 54h/D4h/154h (slot 12) which are returned immediately with
the most recently received slot 12 data. Writes to offset 54h, D4h, and 154h (primary,
secondary and tertiary codecs), get transmitted across the AC-link in slots 1 and 2 as a
normal register access. Slot 12 is also updated immediately to reflect the data being
written.
The controller will not issue back to back reads. It must get a response to the first read
before issuing a second. In addition, codec reads and writes are only executed once
across the link, and are not repeated.
12:
1:0
Bit
15
14
13
3
2
Example
Primary
Access
®
00
1
1
1
X
0
6300ESB ICH implementation of the AC-link, up to three codecs may be
Secondary
Example
Access
®
01
6300ESB ICH implements write posting on I/O writes
X
1
0
0
0
Frame Valid
Slot 1 Valid, Command Address bit (Primary codec
only)
Slot 2 Valid, Command Data bit (Primary codec only)
Slot 3-12 Valid
Reserved
Codec ID (00 reserved for primary; 01 indicate
secondary; 10 indicate tertiary).
Description
Intel
®
6300ESB I/O Controller Hub
Table
140. Slot
269
DS