NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 29

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

Contents—Intel
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22
23
November 2007
Order Number: 300641-004US
20.2
Package Information ............................................................................................. 771
21.1
Electrical Characteristics ....................................................................................... 789
22.1
22.2
22.3
22.4
22.5
Testability ............................................................................................................. 825
20.1.19 Offset 40 - 41h: IDE_TIMP—Primary IDE Timing Register
20.1.20 IDE_TIMS—Secondary IDE Timing Register (SATA–D31:F2) ....................... 750
20.1.21 Offset 44h: SIDETIM—Slave IDE Timing Register
20.1.22 Offset 48h: SDMA_CNT—Synchronous DMA Control Register (SATA–D31:F2) 751
20.1.23 Offset 4A - 4Bh: SDMA_TIM—Synchronous DMA Timing Register (SATA–D31:F2)
20.1.24 Offset 54h: IDE_CONFIG—IDE I/O Configuration Register (SATA–D31:F2) ... 754
20.1.25 Offset 70 - 71h: PID—PCI Power Management Capability ID (SATA–D31:F2) 755
20.1.26 Offset 72 - 73h: PC—PCI Power Management Capabilities (SATA–D31:F2) ... 755
20.1.27 Offset 74 - 75h: PMCS—PCI Power Management Control and Status (SATA–
20.1.28 Offset 80 - 81h: MID—Message Signaled Interrupt Identifiers (SATA–D31:F2) ....
20.1.29 Offset 82 - 83h: MC—Message Signaled Interrupt Message Control (SATA–
20.1.30 Offset 84 - 87h: MA—Message Signaled Interrupt Message Address (SATA–
20.1.31 Offset 88 - 89h: MD—Message Signaled Interrupt Message Data (SATA–D31:F2)
20.1.32 Offset 90h: MAP—Address Map (SATA–D31:F2)........................................ 759
20.1.33 Offset 92h: PCS—Port Status and Control (SATA–D31:F2) ......................... 760
20.1.34 Offset A0h: SRI—SATA Registers Index (SATA–D31:F2) ............................ 760
20.1.35 Offset A4h - A7h: SRD—SATA Registers Data
20.1.36 STTT—SATA TX Termination Test Register A
20.1.37 STOT — SATA TX Output Test Register (SATA–D31:F2) ............................. 762
20.1.38 Offset Index 54h - 57h: SER0—SATA SError Register Port 0 (SATA–D31:F2) 763
20.1.39 Offset Index 64h - 67h: SER1—SATA SError Register Port 1 (SATA–D31:F2) 763
20.1.40 Offset E0h - E3h: BFCS—BIST FIS Control/Status Register (SATA–D31:F2) .. 763
20.1.41 Offset E4h - E7h: BFTD1—BIST FIS Transmit Data1 Register (SATA–D31:F2)765
20.1.42 Offset E8h - EBh: BFTD2—BIST FIS Transmit Data2 Register (SATA–D31:F2)766
Bus Master IDE I/O Registers (D31:F2) .............................................................. 766
20.2.1 BMIC[P,S]—Bus Master IDE Command Register (D31:F2) .......................... 767
20.2.2 BMIS[P,S]—Bus Master IDE Status Register (D31:F2) ............................... 768
20.2.3 BMID[P,S]—Bus Master IDE Descriptor Table Pointer Register (D31:F2)....... 769
Ball Location ................................................................................................... 771
Absolute Maximum Ratings ............................................................................... 789
Functional Operating Range .............................................................................. 789
DC Characteristics ........................................................................................... 790
AC Characteristics ........................................................................................... 796
Timing Diagrams and Test Conditions................................................................. 813
22.5.1 PCI-X ................................................................................................. 813
22.5.2 System Clocks and General Timing ......................................................... 815
22.5.3 IDE and Ultra ATA Timing ...................................................................... 817
22.5.4 USB.................................................................................................... 820
22.5.5 SMBus ................................................................................................ 821
22.5.6 Power and Reset .................................................................................. 822
22.5.7 AC’97 and Miscellaneous ....................................................................... 824
®
6300ESB ICH
(SATA–D31:F2).................................................................................... 748
(SATA–D31:F2).................................................................................... 750
752
D31:F2)756
757
D31:F2)757
D31:F2)758
759
(SATA–D31:F2).................................................................................... 761
(SATA–D31:F2).................................................................................... 762
Intel
®
6300ESB I/O Controller Hub
DS
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