NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 519

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

11—Intel
Table 420. PORTSC- Port N Status and Control (Sheet 2 of 4)
November 2007
Order Number: 300641-004US
11:1
Bits
Default Value:
0
9
8
Device:
®
Offset:
6300ESB ICH
Line Status
Port Reset
Reserved
29
Port 0:CAPLENGTH+44-47h
Port 1: CAPLENGTH+48-4Bh
Port 2: CAPLENGTH+4C-4Fh
Port 3: CAPLENGTH+50-53h
00003000h
Name
These bits reflect the current logical levels of the D+ (bit 11)
and D- (bit 10) signal lines. These bits are used for detection
of low-speed USB devices prior to the port reset and enable
sequence. This field is valid only when the port enable bit is
’0’ and the current connect status bit is set to a ’1’.
The encoding of the bits are:
Bits[11:10] Meaning
reset
reset
of
EHCI
Reserved. This bit will return a ’0’ when read.
Default = 0
1 = Port is in Reset.
0 = Port is not in Reset.
When software writes a ’1’ to this bit from a ’0’, the bus reset
sequence as defined in the USB Specification Revision 2.0 is
started. Software writes a ’0’ to this bit to terminate the bus
reset sequence. Software must keep this bit at a ’1’ long
enough to ensure the reset sequence, as specified in the USB
Specification Revision 2.0, completes.
NOTE: When software writes this bit to a ’1’, it must also
For example: If the port detects that the attached device is
high-speed during reset, then the host controller must have
the port in the enabled state within 2ms of software writing
this bit to a ’0’. The HCHalted bit in the USBSTS register
should be a ’0’ before software attempts to use this bit. The
host controller may hold Port Reset asserted to a ’1’ when the
HCHalted bit is a ’1’. This field is ’0’ if Port Power is ’0’.
Warning:System software should not attempt to reset a port
00
10
01
11
write a ’0’ to the Port Enable bit. When software writes
a ’0’ to this bit there may be a delay before the bit
status changes to a ’0’. The bit status will not read as
a ’0’ until after the reset has completed. When the
port is in high-speed mode after reset is complete, the
host controller will automatically enable this port
(e.g., set the Port Enable bit to a ’1’). A host controller
must terminate the reset and stabilize the state of the
port within 2 milliseconds of software transitioning
this bit from a ’1’ to a ’0’.
when the HCHalted bit in the USBSTS register is a
’1’. Doing so will result in undefined behavior.
SE0 - Not Low-speed device, perform EHCI
J-state - Not Low-speed device, perform EHCI
K-state - Low speed device, release ownership
port
Undefined - Not Low-speed device, perform
reset
Description
Attribute:
Function:
Size:
7
Read/Write
32-bit
Intel
®
6300ESB I/O Controller Hub
Access
R/W
RO
519
DS