NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 386

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

8.8.1.2
Table 273. Offset A2h: GEN_PMCON_2—General PM Configuration 2 Register
Intel
DS
386
Bits
Default Value:
7:5
4
3
2
1
0
®
6300ESB I/O Controller Hub
Lockable:
Note: Usage: ACPI or Legacy.
Device:
CPU Thermal Trip Status
Offset:
PWROK_FLR: PWROK
System Reset Status
CPUPWR_FLR: CPU
Power Failure
Offset A2h: GEN_PMCON_2—General PM Configuration 2
Register
(PM—D31:F0)
(PM—D31:F0)
Reserved
Reserved
Failure
31
A2h
00h
No
Name
(SRS)
(CTS)
Reserved.
The Intel
button is pressed. BIOS is expected to read this bit and clear
it when it is set. This bit is also reset by RSMRST# and CF9h
resets. SRS bit is set only when the system is in S0 or S1
state.
This bit is set when PXPCIRST# is inactive and
CPUTHRMTRIP# goes active while the system is in an S0 or
S1 state. This bit is also reset by RSMRST# and CF9h resets.
It is not reset by the shutdown and reboot associated with the
CPUTHRMTRIP# event.
Reserved.
0 = Software clears this bit by writing a 0 to the bit position.
1 = Indicates that the PWRGD signal from the CPU’s VRM
Software clears this bit by writing a 0 to this bit position.
0 = Software clears this bit by writing a 1 to the bit position,
1 = This bit will be set any time PWROK goes low, when the
NOTE: Traditional designs have a reset button logically OR’d
NOTE: In the case of true PWROK failure, PWROK will go low
went low.
or when the system goes into a G3 state.
system was in S0, or S1 state. The bit will be cleared only
by software by writing a 1 to this bit or when the system
goes to a G3 state.
with the PWROK signal from the power supply and the
CPU’s voltage regulator module. When this is done
with the Intel
be set. The Intel
as though the RSMRST# signal had gone active.
However, it is not treated as a full power failure. When
PWROK goes inactive and then active (but RSMRST#
stays high), the Intel
(regardless of the state of the AFTERG3 bit). When
the RSMRST# signal also goes low before PWROK
goes high, this is a full power failure and the reboot
policy is controlled by the AFTERG3 bit.
first before PWRGD.
®
6300ESB ICH sets this bit when the SYS_RESET#
®
6300ESB ICH, the PWROK_FLR bit will
Power Well:
®
Description
Attribute:
Function:
6300ESB ICH treats this internally
®
Size:
6300ESB ICH will reboot
0
Read-Only Clear
8-bit
Resume
Order Number: 300641-004US
Intel
®
6300ESB ICH—8
November 2007
Access
R/WC
R/WC
R/WC
R/WC