NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 696

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

Table 625. Immediate Terminations of Completion Required Cycles to PCI/PCI-X
Table 626. Immediate Terminations of Posted Write Cycles to PCI/PCI-X
18.9.2
Table 627. Split Terminations of Completion Required Cycles to PCI-X (Sheet 1 of
Intel
DS
696
®
6300ESB I/O Controller Hub
Behavior of Hub Interface Initiated Cycles to PCI-
X Receiving Split Terminations
The behavior described in the following table is independent of the Master Abort Mode
bit and whether or not the cycle is exclusive (locked) or not. The Intel
returns all ’1’s on all data bytes for a read completion that terminates in either Master
Abort or Target Abort on the Hub Interface. Note that when a target or master abort is
returned on the Hub Interface, the attached PCI/PCI-X bus is not locked. This is of
special importance to the completion messages of “data parity error”, “byte count out
of range”, “write data parity error”, “device specific”, and reserved/illegal codes. The
Intel
explicitly master or target aborts on the PCI-X interface.
2)
Successful
Master Abort
Target Abort
† The Master Data Parity Error bit is set only when a data parity error is encountered on the PCI/PCI-X bus.
Successful
Master Abort
Master Abort
Target Abort
Successful
Master Abort
Target Abort
Write Data Parity Error
Byte Count Out Of
Range
®
Termination
PCI-X Split
Termination
PCI/PCI-X
6300ESB ICH must not lock its bus on these errors, even though they are not
Class
N/A
1
0
N/A
MAM Bit
0
1
1
1
2
Message
Successful
Master Abort
Target Abort
Index
00h
00h
01h
02h
00h
None
Generate NMI/SMI
None
Generate NMI/SMI
as enabled
Successful
Master Abort
Target Abort
Target Abort
Target Abort
Hub Interface
Completion
Action
Received Target Abort (Sec)
Signaled Target Abort (Pri)
Master Data Parity Error (Sec)
Master Data Parity Error (Sec)
Received Master Abort (Sec)
Master Data Parity Error (Sec),
when encountered
Received Master Abort (Sec)
Received Target Abort (Sec)
Signaled Target Abort (Pri)
Master Data Parity Error (Sec)
Signaled Target Abort (Pri)
Signaled Target Abort (Pri)
None
Received Master Abort (Sec)
Signaled System Error (Pri)
Received Master Abort (Sec)
Received Target Abort (Sec)
Signaled System Error (Pri)
Status Register Bits Set
Status Register Bits Set
Order Number: 300641-004US
Intel
®
®
6300ESB ICH—18
6300ESB ICH
November 2007
†
†