NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 474

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

Table 371. Offset 00 - 01h: USBCMD—USB Command Register (Sheet 1 of 3)
Intel
DS
474
15:7
Bits
Default Value:
8
7
6
5
4
®
6300ESB I/O Controller Hub
Device:
Offset:
Loop Back Test Mode
Force Global Resume
Configure Flag (CF)
Max Packet (MAXP)
Software Debug
(SWDBG)
Reserved
29
00-01h
0000h
Name
(FGR)
Reserved.
0 = Disable loop back test mode.
1 = The Intel
This bit selects the maximum packet size that may be used
for full-speed bandwidth reclamation at the end of a frame.
This value is used by the Host Controller to determine
whether it should initiate another transaction based on the
time remaining in the SOF counter. Use of reclamation
packets larger than the programmed size will cause a Babble
error when executed during the critical window at frame end.
The Babble error results in the offending endpoint being
stalled. Software is responsible for ensuring that any packet
that could be executed under bandwidth reclamation be
within this size limit.
0 = 32 bytes
1 = 64 bytes
This bit has no effect on the hardware. It is provided only as a
semaphore service for software.
0 = Indicates that software has not completed host controller
1 = HCD software sets this bit as the last action in its process
The SWDBG bit must only be manipulated when the controller
is in the stopped state. This may be determined by checking
the HCHalted bit in the USBSTS register.
0 = Normal Mode.
1 = Debug mode. In SW Debug mode, the Host Controller
0 = Software resets this bit to ’0’ after 20 ms has elapsed to
1 = Host Controller sends the Global Resume signal on the
both ports are connected together, a write to one port will
be seen on the other port, and the data will be stored in
I/O offset 18h.
configuration.
of configuring the Host Controller.
clears the Run/Stop bit after the completion of each USB
transaction. The next transaction is executed when
software sets the Run/Stop bit back to ‘1’.
stop sending the Global Resume signal. At that time, all
USB devices should be ready for bus activity. The ’1’ to ’0’
transition causes the port to send a low speed EOP signal.
This bit will remain a ’1’ until the EOP has completed.
USB and sets this bit to ’1’ when a resume event
(connect, disconnect, or K-state) is detected while in
global suspend mode.
®
6300ESB ICH is in loop back test mode. When
Description
Attribute:
Function:
Size:
0/1
Read/Write
16-bit
Order Number: 300641-004US
Intel
®
6300ESB ICH—10
November 2007
Access
R/W
R/W
R/W
R/W
R/W