NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 536

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

Intel
DS
536
Bits
Default Value:
2
1
0
®
Table 440. Offset 00h: HST_STS—Host Status Register (Sheet 2 of 2)
6300ESB I/O Controller Hub
Device:
Offset:
HOST_BUSY
DEV_ERR
31
00h
00h
Name
INTR
0 = Software resets this bit by writing a ’1’ to this location.
1 = The source of the interrupt or SMI# was due to one of the
This bit may be set only by termination of a command. INTR
is not dependent on the INTREN bit of the Host Controller
Register (offset 02h). It is only dependent on the termination
of the command. When the INTREN bit is not set, the INTR bit
will be set, although the interrupt will not be generated.
Software may poll the INTR bit in this non-interrupt case.
0 = Software resets this bit by writing ’1’ to this location. The
1 = The source of the interrupt or SMI# was the successful
0 = Cleared by the Intel
1 = Indicates that the Intel
The Intel
or SMI#.
following:
- Illegal Command Field
- Unclaimed Cycle (host initiated)
- Host Device Time-out Error
- CRC Error
Intel
SMI#.
completion of its last command.
transaction is completed.
command from the host interface. No SMB registers
should be accessed while this bit is set, except the BLOCK
DATA BYTE Register. The BLOCK DATA BYTE Register may
be accessed when this bit is set only when the SMB_CMD
bits in the Host Control Register are programmed for
Block command or I
in order to check the BYTE_DONE_STS bit.
®
6300ESB ICH will then deassert the interrupt or
®
6300ESB ICH will then deassert the interrupt
®
2
Description
C Read command. This is necessary
Attribute:
Function:
6300ESB ICH when the current
®
6300ESB ICH is running a
Size:
3
Read/Write Clear
8-bit
Order Number: 300641-004US
Intel
®
6300ESB ICH—12
November 2007
(special)
Access
R/WC
R/WC
RO