NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 466

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

Table 360. Offset 0Dh: MLT—Master Latency Timer
10.1.10 Offset 0Eh: HTYPE—Header Type Register
Table 361. Offset 0Eh: HTYPE—Header Type Register (USB—D29:F0/F1)
Intel
DS
466
Bits
Bits
Default Value:
Default Value:
6:0
7
®
6300ESB I/O Controller Hub
Note: For function 1, this register is hard-wired to 00h. For function 0, bit 7 is determined by
Device:
Device:
Offset:
Offset:
Configuration Layout
Multi-Function Bit
(USB—D29:F0/F1)
the values in bits 15 and 9 of the function disable register (D31:F0:F2h).
29
0Dh
00h
Name
29
0Eh
FN 0: 80h
FN 1: 00h
Name
MLT
These bits are fixed at ‘0’.
Multi-Function Device — RO.
0 = Single-function device.
1 = Multi-function device.
Since the upper functions in this device can be individually
hidden, this bit is based on the function-disable bits in Device
31, Function 0, Offset F2h as follows:
Hardwired to 00h, which indicates the standard PCI
configuration layout.
D29:F0
(Bit 15)
X
X
0
1
D29:F1
(Bit 9)
X
X
0
1
Multi-Function
Description
Description
Bit
Attribute:
Attribute:
1
1
1
0
Function:
Function:
Size:
Size:
0/1
Read-Only
8-bit
0/1
Read-Only
8-bit
Order Number: 300641-004US
Intel
®
6300ESB ICH—10
November 2007
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