NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 477

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

10—Intel
Table 372. Run/Stop, Debug Bit Interaction SWDBG (Bit 5), Run/Stop (Bit 0)
November 2007
Order Number: 300641-004US
®
6300ESB ICH
Operation
When the USB Host Controller is in Software Debug Mode (USBCMD Register bit 5=1),
the single stepping software debug operation is as follows:
To Enter Software Debug Mode:
In Software Debug mode, when the Run/Stop bit is set, the Host Controller starts.
When a valid TD is found, the Run/Stop bit is reset. When the TD is finished, the
HCHalted bit in the USBSTS register (bit 5) is set.
The SW Debug mode skips over inactive TDs and only halts after an active TD has been
executed. When the last active TD in a frame has been executed, the Host Controller
waits until the next SOF is sent and then fetches the first TD of the next frame before
halting.
This HCHalted bit may also be used outside of Software Debug mode to indicate when
the Host Controller has detected the Run/Stop bit and has completed the current
transaction. Outside of the Software Debug mode, setting the Run/Stop bit to ’0’
10. HCD sets Run/Stop bit to ‘1’ to resume normal schedule execution.
1. HCD puts Host Controller in Stop state by setting the Run/Stop bit to ‘0’.
2. HCD puts Host Controller in Debug Mode by setting the SWDBG bit to ‘1’.
3. HCD sets up the correct command list and Start Of Frame value for starting point in
4. HCD sets Run/Stop bit to ’1’.
5. Host Controller executes next active TD, sets Run/Stop bit to ‘0’ and stops.
6. HCD reads the USBCMD register to check if the single step execution is completed
7. HCD checks results of TD execution. Go to step 4 to execute next TD or step 8 to
8. HCD ends Software Debug mode by setting SWDBG bit to ‘0’.
9. HCD sets up normal command list and Frame List table.
SWDBG
(Bit 5)
the Frame List Single Step Loop.
(HCHalted = 1).
end Software Debug mode.
0
0
1
1
Run/Stop
(Bit 0)
0
1
0
1
When executing a command, the Host Controller completes the
command and then stops. The 1.0 ms frame counter is reset and
command list execution resumes from start of frame using the frame
list pointer selected by the current value in the FRNUM register. (While
Run/Stop = 0, the FRNUM register may be reprogrammed).
Execution of the command list resumes from Start Of Frame using the
frame list pointer selected by the current value in the FRNUM register.
The Host Controller remains running until the Run/Stop bit is cleared
(by software or hardware).
When executing a command, the Host Controller completes the
command and then stops and the 1.0 ms frame counter is frozen at
its current value. All statuses are preserved. The Host Controller
begins execution of the command list from where it left off when the
Run/Stop bit is set.
Execution of the command list resumes from where the previous
execution stopped. The Run/Stop bit is set to ’0’ by the Host
Controller when a TD is being fetched. This causes the Host Controller
to stop again after the execution of the TD (single step). When the
Host Controller has completed execution, the HC Halted bit in the
Status Register is set.
Description
Intel
®
6300ESB I/O Controller Hub
477
DS