NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 690

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

18.7.9.1.5 Write Transactions on Hub Interface – Intel
18.7.9.1.6 Write Transactions on PCI – Intel
18.7.9.1.7 Write Transactions on PCI – Intel
18.7.9.2 System Errors
18.7.9.2.1 PCI SERR# Pin Assertion
18.7.9.2.2 Other System Errors
Intel
DS
690
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6300ESB I/O Controller Hub
Interface Master
There is no way of detecting that a northern device detected a parity error from a Hub
Interface posted write from PCI. Therefore, no action is taken by the Intel
ICH.
When the Intel
When a data parity error is reported on the PCI bus from a Hub Interface or PCI peer
initiated write request by the target’s assertion of PERR#, the Intel
When SERR# is sampled asserted, the Intel
error bit in the secondary status register. The Intel
(depending on which is enabled) when:
The Intel
following reasons:
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Forwards the bad parity with the data to PCI when decoded by the bridge.
Generates NMI/SMI (depending on which is enabled) and sets the signaled system
error bit (bit 14) in the Primary status register, when the parity error response bit
(bit 6) is set in the command register.
Asserts PERR# two cycles after the data transfer, when the secondary interface
parity error response bit is set in the bridge control register.
Sets the secondary interface parity error detected bit in the secondary status
register.
Forces bad parity error condition to the primary bus.
Sets the Detected Parity Detected bit in the secondary status register (bit 8 of
offset 1E-1Fh), when the secondary interface parity error response bit is set in the
bridge control register.
Generates NMI/SMI (depending on which is enabled) and sets the signaled system
error bit in the status register, when all of the following conditions are met:
The SERR# forward enable bit is set in the bridge control register, and
The primary SERR# enable bit is set in the Primary command register.
Master timeout on delayed transaction when the primary SERR# enable bit is set
and SERR# due to timeout enable bit (bit 11 of offset 3E-3Fh) is set.
The MAM bit (Master Abort Mode) is set in the bridge control register and a posted
write from the Hub Interface results in a master abort on PCI, or a posted write
from one PCI interface results in a master abort on the other PCI interface. (No
— The SERR# enable bit is set in the command register.
— The secondary interface parity error response bit is set in the bridge control register.
— The primary interface parity error response bit is set in the command register.
— The Intel
parity error was not forwarded from the Hub Interface).
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6300ESB ICH also conditionally NMI or SMI as enabled for any of the
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6300ESB ICH detects a data parity error on a PCI write, it:
6300ESB ICH did not detect the parity error on the Hub Interface (i.e., the
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6300ESB ICH as PCI Target
6300ESB ICH as PCI Master
6300ESB ICH sets the received system
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6300ESB ICH generates NMI/SMI
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6300ESB ICH as a Hub
Order Number: 300641-004US
Intel
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6300ESB ICH:
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6300ESB ICH—18
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November 2007
6300ESB