NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 57

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

3—Intel
3.3
Table 5.
November 2007
Order Number: 300641-004US
®
6300ESB ICH
PCI Interface
PCI Interface Signals (Sheet 1 of 3)
AD[31:0]
C/
BE[3:0]#
DEVSEL#
FRAME#
IRDY#
Signal
Name
Type
I/O
I/O
I/O
I/O
I/O
PCI Address/Data: AD[31:0] signals are multiplexed. During the first
clock of a transaction, AD[31:0] contain the physical address (32 bits).
After the first clock, AD[31:0] contain data.
Bus Command and Byte Enables: The command and byte enable
signals are multiplexed. During the address phase of a transaction, C/
BE[3:0]# define the bus command. During the data phase C/BE[3:0]#
are used as Byte Enables. All command encoding not shown are reserved.
C/BE[3:0]# Command Type Comment
0 0 0 0 Interrupt Acknowledge
0 0 0 1 Special Cycle
0 0 1 0 I/O Read
0 0 1 1 I/O Write
0 1 1 0 Memory Read
0 1 1 1 Memory Write
1 0 1 0 Configuration Read
1 0 1 1 Configuration Write
1 1 0 0 Memory Read Multiple
1 1 0 1 DAC Mode Address to be latched (target only)
1 1 1 0 Memory Read Line
1 1 1 1 Memory Write and Invalidate
The Intel
respond if a PCI master generates a cycle using a reserved value. See PCI
section for details on how these commands are supported depending on
the Intel
As a target, the Intel
for 44 bits.
Device Select: The Intel
transaction. As an output, the Intel
when a PCI master peripheral attempts an access to an internal Intel
6300ESB ICH address or an address destined for Hub Interface (main
memory or AGP). As an input, DEVSEL# indicates the response to an
Intel
stated from the leading edge of PXPCIRST#. DEVSEL# remains tri-stated
by the Intel
Cycle Frame: FRAME# is driven by the current Initiator to indicate the
beginning and duration of an access. While FRAME# is asserted data
transfers continue. When FRAME# is negated the transaction is in the
final data phase. FRAME# is an input to the Intel
is the Target. FRAME# is an output when the Intel
initiator. FRAME# remains tri-stated by the Intel
driven as an initiator.
Initiator Ready: IRDY# indicates the Intel
Initiator, to complete the current data phase of the transaction. It is used
in conjunction with TRDY#. A data phase is completed on any clock both
IRDY# and TRDY# are sampled asserted. During a write, IRDY# indicates
the Intel
read, it indicates the Intel
IRDY# is an input to the Intel
ICH is the Target and an output when the Intel
Initiator. IRDY# remains tri-stated by the Intel
driven as an initiator.
®
6300ESB ICH-initiated transaction on the PCI bus. DEVSEL# is tri-
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®
®
6300ESB ICH’s role in the PCI cycle (target or initiator).
6300ESB ICH has valid data present on AD[31:0]. During a
6300ESB ICH will not use reserved values, and will not
®
6300ESB ICH until driven as a target.
®
6300ESB ICH can support DAC mode addressing
®
®
6300ESB ICH asserts DEVSEL# to claim a PCI
6300ESB ICH is prepared to latch data.
®
Description
6300ESB ICH when the Intel
®
6300ESB ICH asserts DEVSEL#
®
Intel
6300ESB ICH’s ability, as an
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®
®
®
®
6300ESB ICH until
6300ESB ICH is an
6300ESB I/O Controller Hub
®
6300ESB ICH until
6300ESB ICH when it
6300ESB ICH is the
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6300ESB
®
DS
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