NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 669

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

18—Intel
November 2007
Order Number: 300641-004US
Bits
06
05
04
03
Table 604. Offset 3E: BCTRL—Bridge Control (Sheet 2 of 3)
VGA Enable
Abort Mode
®
VGA 16-bit
Secondary
Device
Bus Reset
Offset
Decode
(VGAE)
6300ESB ICH
Master
Name
(MAM)
(SBR)
28
3E
Controls PXPCIRST# assertion on PCI-X bus when SBRE is
set. See
Compensation Register”
1 = The Intel
0 = The Intel
Controls the Intel
abort occurs on either interface.
Master Abort on Hub Interface:
When 0: The Intel
drives all '1's for reads and discards data on writes.
When 1: The Intel
PCI-X.
Master Abort PCI/PCI-X: (Completion required packets
only)
When 0: Normal completion status is returned on the Hub
Interface.
When 1: Target abort completion status is returned on the
Hub Interface.
Enables the bridge to provide 16 bits decoding of VGA I/O
address precluding the decode of VGA alias addresses every 1
KB. This bit requires the VGA enable bit (bit 3 of this register)
to be set 1.
Modifies the Intel
compatible address. When set to a 1, the Intel
forwards the following transactions from the Hub Interface to
PCI-X regardless of the value of the I/O base and limit
registers. The transactions are qualified by the memory
enable and I/O enable in the command register.
Memory addresses: 000A0000h-000BFFFFh
I/O addresses: 3B0h-3BBh and 3C0h-3DFh. For the I/O
addresses, bits [63:16] of the address must be 0, and bits
[15:10] of the address are ignored (i.e., aliased).
The same holds true from secondary accesses to the primary
interface in reverse. That is, when the bit is 0, memory and I/
O addresses on the secondary interface between the above
ranges are forwarded to the Hub Interface.
PCIXSBRST# is asserted, the data buffers between the
Hub Interface and PCI-X and the PCI-X bus are initialized
back to reset conditions. The Hub Interface and the
configuration registers are not affected. To be effective,
software must keep asserted for at least 100 µsecs.
Section 18.6.1.32, “Offset E4: PCR - PCI
®
®
6300ESB ICH asserts PCIXSBRST#. When
6300ESB ICH de-asserts PCIXSBRST#
®
®
®
®
6300ESB ICH's response to VGA
6300ESB ICH's behavior when a master
6300ESB ICH asserts TRDY# on PCI-X. It
6300ESB ICH returns a target abort on
Description
for SBRE details.
Attribute:
Function
Size:
®
6300ESB ICH
0
Read/Write
16-bit
Intel
®
Reset
Value
6300ESB I/O Controller Hub
0
0
0
0
Access
R/W
R/W
R/W
R/W
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