NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 444

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

9.1.15
Intel
DS
444
31:1
Bits
Default Value:
9:4
2:1
0
3
0
®
Table 337. Offset 24h - 27h: CPBA – IDE Command Posting Base Address
6300ESB I/O Controller Hub
Note: The Intel
Device:
Hardwired Base Address
Offset:
RTE – Resource Type
Base Address
Prefetchable
Offset 24h - 27h: CPBA – IDE Command Posting
Base Address
accesses. This is much more than is needed; by requesting this much space, decoding
may be simplified. In addition to the standard PCI Memory Space Enable bit, the
Command Posting Enable bits in the IDE I/O Configuration register must be set for the
Intel
Indicator
31
24h-27h
00000000h
Name
Type
®
6300ESB ICH to properly decode the accesses to this range.
®
6300ESB ICH requests 1 Kbyte of memory space for the Command Posting
Base address of the IDE Command Posting memory space
(aligned to 1 Kbyte).
These bits are hardwired to ‘0’ to indicate that the size of the
range requested is 1 Kbyte.
Hard-wired to ‘0’, indicating that this range is not pre-
fetchable.
Hard-wired to “00”, indicating that this range may be mapped
anywhere in 32-bit address space.
This bit is hard-wired to ‘0’, indicating a request for memory
space.
Description
Attribute:
Function:
Size:
1
Read/Write
32-bit
Order Number: 300641-004US
Intel
®
6300ESB ICH—9
November 2007
Access
R/W
RO
RO
RO
RO