NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 17

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

Contents—Intel
November 2007
Order Number: 300641-004US
8.2
8.3
8.4
8.5
8.6
8.7
8.1.37 Offset F4: ETR1—PCI-X Extended Features Register
8.1.38 Offset F8h: Manufacturer’s ID ................................................................ 345
DMA I/O Registers ........................................................................................... 346
8.2.1
8.2.2
8.2.3
8.2.4
8.2.5
8.2.6
8.2.7
8.2.8
8.2.9
8.2.10 DMA_CLMSK—DMA Clear Mask Register .................................................. 354
8.2.11 DMA_WRMSK—DMA Write All Mask Register ............................................ 355
Timer I/O Registers ......................................................................................... 355
8.3.1
8.3.2
8.3.3
8259 Interrupt Controller (PIC) Registers ........................................................... 360
8.4.1
8.4.2
8.4.3
8.4.4
8.4.5
8.4.6
8.4.7
8.4.8
8.4.9
8.4.10 ELCR1—Master Controller Edge/Level Triggered Register ........................... 367
8.4.11 ELCR2—Slave Controller Edge/Level Triggered Register ............................. 367
Advanced Interrupt Controller (APIC0) ............................................................... 368
8.5.1
8.5.2
8.5.3
8.5.4
8.5.5
8.5.6
8.5.7
8.5.8
8.5.9
8.5.10 Offset 10h - 11h (Vector 0) through 3E - 3Fh (Vector 23): Redirection Table 373
Real Time Clock Registers................................................................................. 375
8.6.1
8.6.2
8.6.3
CPU Interface Registers.................................................................................... 381
8.7.1
8.7.2
8.7.3
®
6300ESB ICH
(LPC I/F—D31:F0) ................................................................................ 345
8.3.1.1
8.3.1.2
8.6.2.1
8.6.2.2
8.6.2.3
DMABASE_CA—DMA Base and Current Address Registers .......................... 348
DMABASE_CC—DMA Base and Current Count Registers ............................. 349
DMAMEM_LP—DMA Memory Low Page Registers ....................................... 350
DMACMD—DMA Command Register ........................................................ 350
DMASTA—DMA Status Register .............................................................. 351
DMA_WRSMSK—DMA Write Single Mask Register...................................... 352
DMACH_MODE—DMA Channel Mode Register ........................................... 352
DMA Clear Byte Pointer Register............................................................. 353
DMA Master Clear Register .................................................................... 354
TCW —Timer Control Word Register ........................................................ 356
SBYTE_FMT—Interval Timer Status Byte Format Register........................... 358
Counter Access Ports Register ................................................................ 360
Interrupt Controller I/O MAP .................................................................. 360
ICW1—Initialization Command Word 1 Register ........................................ 361
ICW2—Initialization Command Word 2 Register ........................................ 362
ICW3—Master Controller Initialization Command Word 3 Register ............... 363
ICW3—Slave Controller Initialization Command Word 3 Register ................. 363
ICW4—Initialization Command Word 4 Register ........................................ 364
OCW1—Operational Control Word 1 (Interrupt Mask) Register .................... 364
OCW2—Operational Control Word 2 Register ............................................ 365
OCW3—Operational Control Word 3 Register ............................................ 366
APIC Register Map ................................................................................ 368
IND—Index Register ............................................................................. 369
DAT—Data Register .............................................................................. 369
Offset FEC0_0020h: IRQPA—IRQ Pin Assertion Register............................. 370
Offset FEC0 - EOIR: EOI Register ........................................................... 370
Offset 00h: ID—Identification Register .................................................... 371
Offset 01h: VER—Version Register .......................................................... 372
Offset 02h: ARBID—Arbitration ID Register.............................................. 372
Offset 03h: BOOT_CONFIG—Boot Configuration Register ........................... 373
I/O Register Address Map ...................................................................... 375
Indexed Registers ................................................................................ 376
RTC_REGD—Register D (Flag Register).................................................... 380
NMI_SC—NMI Status and Control Register ............................................... 381
NMI_EN—NMI Enable (and Real Time Clock Index) ................................... 382
PORT92—Fast A20 and Init Register ....................................................... 382
RDBK_CMD—Read Back Command ............................................ 357
LTCH_CMD—Counter Latch Command ....................................... 357
RTC_REGA—Register A ............................................................ 377
RTC_REGB—Register B (General Configuration) .......................... 378
RTC_REGC—Register C (Flag Register) ...................................... 380
Intel
®
6300ESB I/O Controller Hub
DS
17