NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 501

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

11—Intel
Table 404. Offset 6C - 6Fh: USB EHCI Legacy Support Extended Control/Status
11.1.27 Offset 70 - 73h: Intel Specific USB EHCI SMI
Table 405. Offset 70 - 73h: Intel Specific USB EHCI SMI (Sheet 1 of 2)
November 2007
Order Number: 300641-004US
31:2
27:2
25:2
Bits
Bits
Default Value:
Default Value:
21
20
4
3
2
1
0
8
6
2
Note: This register provides a mechanism for BIOS to provide USB EHCI related bug fixes and
SMI on USB Error Enable
Device:
Device:
®
Offset:
Offset:
SMI on USB Complete
SMI on Host System
6300ESB ICH
SMI on Port Change
SMI on Frame List
SMI on PortOwner
Rollover Enable
SMI on PMCSR
SMI on Async
Error Enable
(Sheet 2 of 2)
workarounds. Writing a ‘1’ to that bit location clears bits that are marked as Read/
Write-Clear
(R/WC). Software should clear all SMI status bits prior to setting the global SMI enable
bit and individual SMI enable bit to prevent spurious SMI when returning from a
powerdown.
Reserved
Reserved
Enable
Enable
29
6C-6Fh
00000000h
Name
29
70-73h
00000000h
Name
When this bit is a ’1’ and the SMI on Host System Error is a
’1’, the host controller will issue an SMI.
When this bit is a ’1’ and the SMI on Frame List Rollover bit is
a ’1’, the host controller will issue an SMI.
When this bit is a ’1’ and the SMI on Port Change Detect bit is
a ’1’, the host controller will issue an SMI.
When this bit is a ’1’ and the SMI on USB Error bit is a ’1’, the
host controller will issue an SMI immediately.
When this bit is a ‘1’ and the SMI on USB Complete bit is a ’1’,
the host controller will issue an SMI immediately.
Reserved. Hardwired to 00h.
Reserved.
Bits 27:22 correspond to the Port Owner bits for ports 0 (22)
through 3 (25). These bits are set to ‘1’ whenever the
associated Port Owner bits transition from ‘0’->’1’ or ‘1’->’0’.
Software clears these bits by writing a ’1’.
This bit is set to ‘1’ whenever software modifies the Power
State bits in the Power Management Control/Status (PMCSR)
register.
This bit is set to ‘1’ whenever the Async Schedule Enable bit
transitions from ‘1’->’0’ or ‘0’->’1’
Power Well:
Power Well:
Description
Description
Attribute:
Attribute:
Function:
Function:
Size:
Size:
7
Read/Write
32-bit
Suspend
7
Read/Write
32-bit
Suspend
Intel
®
6300ESB I/O Controller Hub
Access
Access
R/WC
R/WC
R/WC
R/WC
R/W
R/W
R/W
R/W
R/W
RO
501
DS