NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 732

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

Table 657. Logical Device 4 (Serial Port 0)
Intel
DS
732
®
6300ESB I/O Controller Hub
Enable
Default = 00h
I/O Base Address
Default = 00h
Primary Interrupt
Select
Default = 00h
Logical Device
Register
Address
60-61h
(R/W)
(R/W)
(R/W)
30h
70h
Bits[7:1] Reserved, set to ’0’.
Bit[0]
1 = Enable the logical device currently selected through
0 = Logical device currently selected is inactive
Registers 60h (MSB) and 61h (LSB) set the base
address for the device.
NOTE: Decode is on 8 Byte boundaries
Intel
3F8 - 3FF (COM 1)
2F8 - 2FF (COM 2)
220 - 227
228 - 22F
238 - 23F
2E8 - 2EF (COM 4)
338 - 33F
3E8 - 3EF (COM 3)
Bits[3:0] select which interrupt level is used for the
primary Interrupt.
00= No interrupt selected
01= IRQ1
02= IRQ2
03= IRQ3
04= IRQ4
05= IRQ5
06= IRQ6
07= IRQ7
08= IRQ8
09= IRQ9
0A= IRQ10
0B= IRQ11
0C= IRQ12
0D= IRQ13
0E= IRQ14
0F= IRQ15
Bits[7:4] Reserved
NOTE: An Interrupt is activated by setting this register
NOTE: Each SIU port must use a dedicated interrupt.
the Logical Device # register.
®
to a non-zero value and setting any combination
of bits 0-3 in the corresponding UART IER and
the OUT2 bit in the MCR
SIU interrupts cannot be shared with each other
or with other devices.
6300ESB ICH Comm Decode Ranges
Description
Order Number: 300641-004US
Intel
®
6300ESB ICH—19
November 2007