NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 432

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

8.10.8
Table 320. Offset GPIOBASE + 34h: GP_IO_SEL2—GPIO Input/Output Select 2
8.10.9
Table 321. Offset GPIOBASE + 38h: GP_LVL2—GPIO Level for Input or Output 2
Intel
DS
432
Implementation Note: Bits 26:31 may be in CORE Well.
31:2
25:2
23:1
11:0
31:2
25:2
Bits
Bits
Default Value:
Default Value:
6
4
2
6
4
®
6300ESB I/O Controller Hub
Lockable:
Lockable:
Device:
Device:
Offset:
Offset:
GP_IO_SEL2[43:32]
GP_LVL[57:56]
Offset GPIOBASE + 34h: GP_IO_SEL2—GPIO
Input/Output Select 2 Register
Register
Offset GPIOBASE + 38h: GP_LVL2—GPIO Level for
Input or Output 2 Register
Register
Reserved
31
GPIOBASE +34h
00000000h
No
Name
31
GPIOBASE +38h
00000FFFh
No
Name
Always 0. No corresponding GPIO.
Always 0. Output only.
Always 0. No corresponding GPIO.
When set to a 1, the corresponding GPIO signal (when
enabled in the GPIO_USE_SEL2 register) is programmed as
an input. When set to 0, the GPIO signal is programmed as an
output.
Reserved. Read-only 0.
The GP_LVL[n] bit may be updated by software to drive a
high or low value on the output pin. 1 = high, 0 = low.
NOTE: These output are open drain. Setting this bit to one
Since these bits correspond to GPIO that are in the RTC well,
these bits will be reset by RTCRST#.
does not drive a ‘1’ but allows for an external pullup to
cause a high value on the pin.
Power Well:
Power Well:
Description
Description
Attribute:
Attribute:
Function:
Function:
Size:
Size:
0
Read/Write
32-bit
Core for 23:0;
Resume for 31:24
0
Read/Write
32-bit
Core for 23:0, RTC for 31:24
Order Number: 300641-004US
Intel
®
6300ESB ICH—8
November 2007
Access
Access
RO