NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 66

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

3.7
Table 9.
3.8
Table 10.
Intel
DS
66
®
6300ESB I/O Controller Hub
LPC I/F
LPC Interface Signals
Interrupt Interface
Interrupt Signals (Sheet 1 of 2)
/ FWH[3:0]
NOTE: All LPC/FWH signals are in the core well
NOTE: The Interrupt signals are 5V tolerant except for PXIRQ [3:0]# / GPIO[36:33]
LDRQ[1:0
LFRAME#
LAD[3:0]
PIRQ[D:A]#
FWH[4]
Name
SERIRQ
]#
Name
/
Typ
I/O
I/O
e
I
Type
I/O
LPC Multiplexed Command, Address, Data: Internal pull-ups are
provided.
LPC Frame: Indicates the start of an LPC cycle, or an abort.
LPC Serial DMA/Master Request Inputs: Used by LPC devices, such as
Super I/O chips, to request DMA or bus master access.
I
Serial Interrupt Request: This pin implements the serial interrupt
protocol.
PCI Interrupt Requests: In Non-APIC Mode the PIRQx# signals
may be routed to interrupts 3, 4, 5, 6, 7, 9, 10, 11, 12, 14 or 15 as
described in the Interrupt Steering section. Each PIRQx# line has a
separate Route Control Register.
In APIC mode, these signals are connected to the internal I/O APIC
in the following fashion:
PIRQ[A]# IRQ16
PIRQ[B]# IRQ17
PIRQ[C]# IRQ18
PIRQ[D]# IRQ19
This frees the legacy interrupts. These signals are 5V tolerant.
Description
Description
Order Number: 300641-004US
Intel
®
6300ESB ICH—3
November 2007