NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 700

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

18.10.3 Algorithm (Multiple PCI-X Devices Requesting)
18.10.4 Accesses From Multiple Agents to Same 4K Page
18.11 Internal Bus/Device Communication
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6300ESB I/O Controller Hub
When multiple agents are requesting in PCI-X mode, the definition of T
Instead of just indicating data in buffer, it becomes like T
buffer plus data in flight. When multiple agents are requesting in PCI-X mode, the
Intel
by utilizing its MLT parameter. When the MLT expires, it stops this stream and switches
to another stream.
Differences from P64H algorithm:
In order to avoid the need to track the status of the buffers when multiple agents are
asking for data from the same 4K page, the Intel
when the same PCI master has already established another delayed transaction to that
4K page.
Internally, all devices that reside on the “logical PCI bus” are connected to an internal
bus called “SiBus” (silicon bus). This is a bus architecture developed within PCG that
allows for high code reuse and the ability to connect multiple units together in a
standard manner. It is split transaction based.
By choosing this micro-architecture, cycles may originate from any agent and be
decoded by any other agent. This allows peer-to-peer communication to effectively be
free. For this reason, the SM Bus controller is also connected to this bus, allowing PCI
configuration cycles that originate either from the Hub Interface or SM Bus to use the
same data and control paths to access internal registers.
However, this must be monitored carefully by the micro-architecture. Configuration
cycles from SM Bus must be allowed to reach their destination, even when the Hub
Interface communication to one of the PCI busses is blocked due to a deadlock
condition.
Therefore, the micro-architecture must ensure the following:
5. Wait for B < Ts; launch request of size Rs (truncated by Sb, when necessary).
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Restart timer. Go to step 4.
No connect threshold: as soon as the first data is available in the DT buffer, a PCI
device is allowed to connect.
Allows multiple outstanding reads per DT buffer, (so long as restrict size of all
outstanding reads for a DT buffer to remaining capacity in DT buffer), yielding
smaller prefetch overshoot
Periodic subsequent fetch: smaller, more frequent requests reduce prefetch
overshoot
T
remaining in the DT buffer
Delayed subsequent launch for multi-stream operation to reduce prefetch
overshoot
First subsequent launch threshold
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I
and T
6300ESB ICH needs to switch between these agents for completions. It does this
S
as a low watermark takes into account data in flight; not just data
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6300ESB ICH retries a PCI master
I
, and represents data in
Order Number: 300641-004US
Intel
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S
6300ESB ICH—18
changes.
November 2007