NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 154

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

5.11.6.3 STPCLK# Implementation Notes
Figure 15. Latching Processor I/F Signals with STOPCLK#
Intel
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154
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6300ESB I/O Controller Hub
The processor treats STPCLK# like an interrupt and recognizes it on instruction
boundaries (no INTA cycles are run). When it recognizes STPCLK# active, the processor
stops execution on the next instruction boundary, stops the pre-fetch unit, empties
internal pipelines and write buffers, and generates a Stop-Grant bus cycle before
entering the Stop Grant state. The processor may stop the clock to most of its internal
modules, and no instructions are executed. The processor exits the Stop Grant state
when it is reset, or upon sampling STPCLK# inactive.
The processor will latch transitions on the external interrupt signals (SMI#, NMI, INTR,
and INIT#) while in Stop Grant state. These interrupts are taken after the deassertion
of STPCLK#.
For the Intel
while STPCLK# is active:
These signals should be run through a transparent latch internal to the Intel
ICH. While STPCLK# is inactive (HIGH) these signals propagate to the Intel
ICH's pins and onto the processor as normal. However when STPCLK# is asserted then
these signals are latched so that they may not change until STPCLK# is deasserted.
This ensures that an edge on these signals is seen while the processor has a valid clock.
These signals need to be latched at least 1 HCLK clock before STPCLK# assertion, and
held 16 HCLK clocks after STPCLK# deassertion.
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The Host controller must post Stop-Grant cycles in such a way that the processor
gets an indication of the end of the special cycle prior to the Intel
observing the Stop-Grant cycle. This ensures that the STPCLK# signals stays active
for a sufficient period after the processor observes the response phase.
When in the C1 state and the STPCLK# signal goes active, the processor will
generate a Stop-Grant cycle, and the system should go to the C2 state. When
STPCLK# goes inactive, it should return to the C1 state.
INTR
INIT#
SMI#
NMI
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Pentium
STPCLK#
SMI#, NMI#, INTR
PCICLK
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4 processor, the following edge signals must not transition
T- Latch
SMI#, NMI#, INTR pin
Order Number: 300641-004US
Intel
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6300ESB ICH
6300ESB ICH—5
November 2007
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6300ESB
6300ESB