NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 399

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

8—Intel
Table 288. PROC_CNT—Processor Control Register (Sheet 2 of 2)
November 2007
Order Number: 300641-004US
Bits
Default Value:
7:5
3:1
4
I/O Address:
0
Lockable:
®
Device:
6300ESB ICH
THRM_DTY
THTL_DTY
THTL_EN
Reserved
31
PMBASE + 10h
(ACPI P_BLK)
00000000h
No (bits 7:5 are write
once)
Name
This write-once 3-bit field determines the duty cycle of the
throttling when the thermal override condition occurs. The
duty cycle indicates the approximate percentage of time the
STPCLK# signal is asserted while in the throttle mode. The
STPCLK# throttle period is 1024 PCICLKs. Note that the
throttling only occurs when the system is in the C0 state.
When in the C2 state, no throttling occurs.
There is no enable bit for thermal throttling, because it should
not be disabled. Once the THRM_DTY field is written, any
subsequent writes will have no effect until PXPCIRST# goes
active.
THRM_DTY Throttle ModePCI Clocks
000
001
010
011
100
101
110
111
When set and the system is in a C0 state, it enables a
processor-controlled STPCLK# throttling. The duty cycle is
selected in the THTL_DTY field.
0 = Disable
1 = Enable
This 3-bit field determines the duty cycle of the throttling
when the THTL_EN bit is set. The duty cycle indicates the
approximate percentage of time the STPCLK# signal is
asserted (low) while in the throttle mode. The STPCLK#
throttle period is 1024 PCICLKs.
THRM_DTY Throttle ModePCI Clocks
000
001
010
011
100
101
110
111
Reserved.
50% Default
87.5%
75.0%
62.5%
50%
37.5%
25%
12.5%
50% Default
87.5%
75.0%
62.5%
50%
37.5%
25%
12.5%
Power Well:
Description
Attribute:
Function:
512
896
768
640
512
384
256
128
512
896
768
640
512
384
256
128
Size:
0
Read/Write
32-bit
Core
Intel
®
6300ESB I/O Controller Hub
Access
399
DS