NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 542

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

12.2.8
12.2.9
Intel
DS
542
Bits
Bits
Default Value:
Default Value:
7:0
6:0
7
®
Table 447. Offset 08h: PEC—Packet Error Check Register
Table 448. Offset 09h: RCV_SLVA—Receive Slave Address Register
6300ESB I/O Controller Hub
Lockable:
Device:
Device:
Offset:
Offset:
SLAVE_ADDR
PEC_DATA
Offset 08h: PEC—Packet Error Check Register
Offset 09h: RCV_SLVA—Receive Slave Address
Register
Reserved
31
08h
00h
Name
31
09h
44h
No
Name
This 8-bit register is written with the 8-bit CRC value that is
used as the SMBus PEC data prior to a write transaction. For
read transactions, the PEC data is loaded from the SMBus into
this register and is then read by software. Software must
ensure that the INUSE_STS bit is properly maintained to
avoid having this field overwritten by a write transaction
following a read transaction.
Reserved.
This field is the slave address that the Intel
decodes for read and write cycles. The default is not 0, so the
SMBus Slave Interface may respond even before the
processor comes up or if the processor is dead. This register
is cleared by RSMRST#, but not by PXPCIRST#.
Power Well:
Description
Description
Attribute:
Attribute:
Function:
Function:
Size:
Size:
3
Read/Write
8-bit
3
Read/Write
8-bit
Resume
®
6300ESB ICH
Order Number: 300641-004US
Intel
®
6300ESB ICH—12
November 2007
Access
Access
R/W
R/W