NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 186

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

5.14.4
5.14.4.1 Signal Descriptions
Table 83.
Intel
DS
186
®
6300ESB I/O Controller Hub
Ultra ATA/33 Protocol
Ultra ATA/33 is enabled through configuration register 48h in Device 31:Function 1 for
each IDE device. The IDE signal protocols are significantly different under this mode
than for the 8237 mode. These differences allow the following enhancements to the
transfer:
Ultra ATA/33 is a physical protocol used to transfer data between a Ultra ATA/33
capable IDE controller such as the Intel
capable IDE devices. It utilizes the standard Bus Master IDE functionality and interface
to initiate and control the transfer. Ultra ATA/33 utilizes a “source synchronous”
signaling protocol to transfer data at rates up to 33 Mbytes/s. The Ultra ATA/33
definition also incorporates a Cyclic Redundancy Checking (CRC-16) error checking
protocol.
The Ultra ATA/33 protocol requires no extra signal pins on the IDE connector. It does
redefine a number of the standard IDE control signals when in Ultra ATA/33 mode.
These redefinitions are shown in the following table.
transferring data from the IDE device to the Intel
defined as transferring data from the Intel
UltraATA/33 Control Signal Redefinitions
The DIOW# signal is redefined as STOP for both read and write transfers. This is always
driven by the Intel
as an acknowledgment to stop a request from the IDE device.
The DIOR# signal is redefined as DMARDY# for transferring data from the IDE device
to the Intel
it is ready to transfer data and to add wait-states to the current transaction. The
DIOR# signal is redefined as STROBE for transferring data from the Intel
ICH to the IDE device (write). It is the data strobe signal driven by the Intel
ICH on which data is transferred during each rising and falling edge transition.
The IORDY signal is redefined as STROBE for transferring data from the IDE device to
the Intel
which data is transferred during each rising and falling edge transition. The IORDY
signal is redefined as DMARDY# for transferring data from the Intel
the IDE device (write). It is used by the IDE device to signal when it is ready to transfer
data and to add wait-states to the current transaction.
•
•
•
Standard IDE
Definition
A source synchronous protocol to allow higher data transfer rates of up to 33
Mbytes/s. The device that drives the data lines also drives the data strobe signal.
Both the source and destination may pause the transfer. The source pauses the
burst by not toggling its strobe signal, while the destination pauses the burst by
deasserting a redefined signal, DMARDY#.
16 bit wide CRC error checking, sent from the Intel
device on DDACK# deassertion.
DIOW#
Signal
DIOR#
IORDY
®
6300ESB ICH (read). It is the data strobe signal driven by the IDE device on
®
6300ESB ICH (read). It is used by the Intel
®
Ultra ATA/33
Read Cycle
6300ESB ICH and is used to request that a transfer be stopped or
Definition
DMARDY#
STROBE
STOP
Ultra ATA/33
®
Write Cycle
Definition
DMARDY#
6300ESB ICH and one or more Ultra ATA/33
STROBE
®
STOP
6300ESB ICH to IDE device.
®
6300ESB ICH. Write cycles are
Read cycles are defined as
®
®
6300ESB ICH
6300ESB ICH to the IDE
6300ESB ICH to signal when
Channel
Primary
PDIOW#
PDIOR#
PIORDY
Intel
Signal
Order Number: 300641-004US
®
Intel
®
6300ESB ICH to
®
6300ESB ICH
6300ESB ICH—5
®
Secondary
November 2007
Channel
SDIOW#
6300ESB
®
SDIOR#
SIORDY
Intel
Signal
6300ESB
®