NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 139

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

5—Intel
5.9.1.1
5.9.1.2
5.9.1.3
5.9.1.4
November 2007
Order Number: 300641-004US
Warning:The overflow conditions for leap years and daylight savings adjustments are
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Note: The Intel
Note: The Intel
6300ESB ICH
rollover. See
rollover.
Update Cycles
An update cycle occurs once a second, when the SET bit of register B is not asserted
and the divide chain is properly configured. During this procedure, the stored time and
date will be incremented, overflow will be checked, a matching alarm condition will be
checked, and the time and date will be rewritten to the RAM locations. The update cycle
will start at least 488 µs after the UIP bit of register A is asserted, and the entire cycle
will not take more than 1984 µs to complete. The time and date RAM locations (0-9)
will be disconnected from the external bus during this time.
To avoid update and data corruption conditions, external RAM access to these locations
may safely occur at two times. When an updated-ended interrupt is detected, almost
999 ms is available to read and write the valid time and date. When the UIP bit of
Register A is detected to be low, there is at least 488 µs before the update cycle begins.
based on more than one date or time item. To ensure proper operation when
adjusting the time, the new time and data values should be set at least two
seconds before one of these conditions (leap year, daylight savings time
adjustments) occurs.
Interrupts
The real-time clock interrupt is internally routed within the Intel
the I/O APIC and the 8259. It is mapped to interrupt vector 8. This interrupt does not
leave the Intel
the SERIRQ stream is ignored.
Lockable RAM Ranges
The RTC’s battery-backed RAM supports two 8-byte ranges that may be locked through
the configuration space. When the locking bits are set, the corresponding range in the
RAM will not be readable or writable. A write cycle to those locations will have no effect.
A read cycle to those locations will return an undefined value.
Once a range is locked, the range may be unlocked only by a hard reset, which will
invoke the BIOS and allow it to relock the RAM range.
Century Rollover
The Intel
index offset 09h) transitions form 99 to 00. Upon detecting the rollover, the Intel
6300ESB ICH will set the NEWCENTURY_STS bit (TCOBASE + 04h, bit 7). When the
system is in an S0 state, this will cause an SMI#. The SMI# handler may update
registers in the RTC RAM that are associated with century value. When the system is in
a sleep state (S1-S5) when the century rollover occurs, the Intel
also set the NEWCENTURY_STS bit, but no SMI# is generated. When the system
resumes from the sleep state, BIOS should check the NEWCENTURY_STS bit and
update the century value in the RTC RAM.
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6300ESB ICH supports the ability to generate an SMI# based on a century
6300ESB ICH does not implement month/year alarms.
6300ESB ICH will detect a rollover when the Year byte (RTC I/O space,
Section 5.9.1.4, “Century Rollover”
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6300ESB ICH, nor is it shared with any other interrupt. IRQ8# from
for more information on the century
Intel
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6300ESB I/O Controller Hub
6300ESB ICH both to
6300ESB ICH will
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