NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 192

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

5.15.5
Table 84.
5.15.6
5.16
5.16.1
Intel
DS
192
®
6300ESB I/O Controller Hub
SATA Interrupts
The following table summarizes interrupt behavior for MSI and wire-modes. In the
table “bits” refers to the 4 possible interrupt bits in I/O space, which are: BMISP.PRDIS
(offset 02h, bit 7), BMISP.I (offset 02h, bit 2), BMISS.PRDIS (offset 0Ah, bit 7), and
BMISS.I (offset 0Ah, bit 2). See
for I/O space register details.
SATA MSI vs. PCI IRQ Actions
SATALED#
The SATALED# pin is driven low to indicate SATA drive activity. When SATALED# is
asserted, the LED is active.
Multimedia Event Timers
Overview
This function provides a set of timers that may be used by the operating system. The
timers are defined such that in the future, the OS may be able to assign specific timers
to be used directly by specific applications. Each timer may be configured to cause a
separate interrupt. This specification allows for a block of 32 timers, with support for up
to eight blocks, for a total of 256 timers. However, specific implementations may
include only a subset of these timers.
The Intel
single counter each with its own comparator and value register. Each timer’s counter
increases monotonically. Each individual timer may generate an interrupt when the
value in its value register matches the value in the main counter. Some of the timers
may be enabled to generate a periodic interrupt.
The registers associated with these timers are mapped to a memory space (much like
the I/O APIC). However, it is not implemented as a standard PCI function. The BIOS
reports to the operating system the location of the register space. The hardware may
support an assignable decode space, however the BIOS will set this space prior to
handing it over to the OS (see
OS will move the location of these timers once it is set by the BIOS.
In the Intel
counter and three timers (comparators). Future devices may have a different number
of implemented timers. Various capabilities registers indicate the number of timers and
the capabilities of each.
All bits are ‘0’.
One or more bits set to ‘1’.
One or more bits set to ‘1’, new bit gets set to ‘1’.
One or more bits set to ‘1’, software clears some
(but not all) bits.
One or more bits set to ‘1’, software clears all bits.
Software clears one or more bits, and one or more
bits is set simultaneously.
®
6300ESB ICH provides three timers. The three timers are implemented as a
®
6300ESB ICH, one timer block is implemented. The timer block has one
Interrupt Register
Section 6.4, “Memory
Section 20.2, “Bus Master IDE I/O Registers (D31:F2)”
Wire-Mode Action
Wire Inactive
Wire Active
Wire Active
Wire Active
Wire Inactive
Wire Active
Map”). It is not expected that the
Order Number: 300641-004US
Intel
No Action
Send Message
Send Message
Send Message
No Action
Send Message
®
MSI Action
6300ESB ICH—5
November 2007