NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 69

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

3—Intel
Table 12.
3.11
Table 13.
November 2007
Order Number: 300641-004US
®
6300ESB ICH
Power Management Interface Signals (Sheet 2 of 2)
CPU Interface
CPU Interface Signals (Sheet 1 of 2)
NOTE: These signals are all in the RESUME well, except THRM# which is in the core well;
NOTES:
SUS_STAT#
1. The CPU I/F signals (except RCIN#, A20GATE, and FERR#) are on a separate power well. This
2. RCIN# and A20GATE, and FERR# are on in the Core power well.
VRMPWRG
CPUSLP#
/ LPCPD#
SUSCLK
A20M#
saves the external pull-up resistors that were needed on previous chipsets.
FERR#
Name
Name
D
PWROK and RSMRST# which are in the RTC well.
Type
Type
O
O
I
O
O
I
Suspend Status: This signal is asserted by the Intel
to indicate that the system will be entering a low power state soon.
This may be monitored by devices with memory that need to switch
from normal refresh to suspend refresh mode. It may also be used by
other peripherals as an indication that they should isolate their
outputs that may be going to powered-off planes. This signal is called
LPCPD# on the LPC I/F.
Suspend Clock: Output of the RTC generator circuit (32.768 KHz).
SUSCLK will have a duty cycle that may be as low as 30% or as high
as 70%.
Voltage Regulator Power Good: Not implemented in the Intel
6300ESB ICH. Pull this input high to Vcc.
Mask A20: A20M# will go active based on either setting the
appropriate bit in the Port 92h register, or based on the A20GATE
input being active.
Speed Strap: During the reset sequence, the Intel
drives A20M# high when the corresponding bit is set in the
FREQ_STRP register.
CPU Sleep: This signal puts the processor into a state that saves
substantial power compared to Stop-Grant state. However, during
that time, no snoops occur. The Intel
assert the CPUSLP# signal when going to the S1 state. It will go
active for all other sleep states.
Numeric Coprocessor Error: This signal is tied to the coprocessor
error signal on the processor. FERR# is only used when the Intel
6300ESB ICH coprocessor error reporting function is enabled in the
General Control Register (D31:F0:Offset D0.bit 5). When FERR# is
asserted, the Intel
interrupt controller unit. It is also used to gate the IGNNE# signal to
ensure that IGNNE# is not asserted to the processor unless FERR# is
active. FERR# requires an external weak pull-up to ensure a high level
when the coprocessor error function is disabled.
FERR# may optionally be used in some states for notification by the
processor of pending interrupt events.
®
6300ESB ICH generates an internal IRQ13 to its
Description
Description
®
6300ESB ICH may optionally
Intel
®
6300ESB I/O Controller Hub
®
6300ESB ICH
®
6300ESB ICH
®
®
DS
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