NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 34

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

Intel
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100 Endpoint Field ........................................................................................................ 211
101 Token Format ........................................................................................................ 212
102 SOF Packet ............................................................................................................ 212
103 Data Packet Format ................................................................................................ 212
104 Bits Maintained in Low Power States ......................................................................... 216
105 USB Legacy Keyboard/Mouse Control Register Bit Implementation ................................ 217
106 USB Legacy Keyboard State Transitions ..................................................................... 220
107 UHCI vs. EHCI ....................................................................................................... 221
108 EHC Resets............................................................................................................ 223
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6300ESB I/O Controller Hub
Interrupt Message Address Format ........................................................................... 134
Interrupt Message Data Format ................................................................................ 135
Stop Frame Explanation .......................................................................................... 137
Data Frame Format................................................................................................. 137
Configuration Bits Reset By RTCRST# Assertion.......................................................... 140
INIT# Going Active ................................................................................................. 141
NMI Sources .......................................................................................................... 143
DP Signal Differences .............................................................................................. 143
General Power States for Systems Using Intel
State Transition Rules for Intel
System Power Plane ............................................................................................... 148
Causes of SCI ........................................................................................................ 149
Causes of SMI#...................................................................................................... 150
Causes of TCO SMI# ............................................................................................... 151
Break Events ......................................................................................................... 152
Sleep Types ........................................................................................................... 156
Causes of Wake Events ........................................................................................... 156
Transitions Due to Power Failure............................................................................... 158
Transitions Due to Power Button............................................................................... 160
Transitions Due to RI# Signal .................................................................................. 161
Write Only Registers with Read Paths in ALT Access Mode ............................................ 163
PIC Reserved Bits Return Values............................................................................... 165
Register Write Accesses in ALT Access Mode............................................................... 165
Intel
Event Transitions that Cause Messages...................................................................... 172
GPIO Implementation ............................................................................................. 176
IDE Legacy I/O Ports: Command Block Registers (CS1x# Chip Select)........................... 180
IDE Transaction Timings (PCI Clocks) ........................................................................ 181
Interrupt/Active Bit Interaction Definition .................................................................. 185
UltraATA/33 Control Signal Redefinitions ................................................................... 186
SATA MSI vs. PCI IRQ Actions .................................................................................. 192
Legacy Routing ...................................................................................................... 193
Frame List Pointer Bit Description ............................................................................. 196
TD Link Pointer ...................................................................................................... 197
TD Control and Status ............................................................................................. 198
TD Token .............................................................................................................. 200
TD Buffer Pointer.................................................................................................... 201
Queue Head Block .................................................................................................. 201
Queue Head Link Pointer ......................................................................................... 201
Queue Element Link Pointer ..................................................................................... 201
Command Register, Status Register and TD Status Bit Interaction................................. 204
Queue Advance Criteria ........................................................................................... 206
USB Schedule List Traversal Decision Table ................................................................ 207
PID Format ............................................................................................................ 209
PID Types ............................................................................................................. 210
Address Field ......................................................................................................... 210
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6300ESB ICH Clock Inputs ............................................................................. 167
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6300ESB I/O Controller Hub....................................... 147
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6300ESB ICH ...................................... 146
Intel
Order Number: 300641-004US
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6300ESB ICH—Contents
November 2007